updating AMS example

hw/ip_examples/ams/ams.core

@@ -15,7 +15,7 @@ filesets:
     - rtl/ams_reg_pkg.sv
     - rtl/ams_reg_top.sv
     - rtl/ams.sv
-    - "!ams_sim? (rtl/dummy_adc.sv)"
+    - "!ams_sim? (rtl/dummy_myinverter.sv)"
     file_type: systemVerilogSource
 
 targets:

hw/ip_examples/ams/analog/control.init

@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-choose xa ../../../hw/ip_examples/ams/analog/adc.sp;
-port_connect -cell ams_adc_1b ( vdd => vdd , gnd => gnd );
-port_dir -cell ams_adc_1b (input sel; output out);
+choose xa ../../../hw/ip_examples/ams/analog/myinverter.sp;
+port_connect -cell myinverter ( vdd => vdd , gnd => gnd );
+port_dir -cell myinverter (input a; output z);
 bus_format <%d>;

hw/ip_examples/ams/analog/myinverter.sp

@@ -0,0 +1,22 @@
+** Copyright EPFL contributors.
+** Licensed under the Apache License, Version 2.0, see LICENSE for details.
+** SPDX-License-Identifier: Apache-2.0
+
+** Uses the 65nm_bulk PTM Bulk CMOS model, February 22, 2006 release
+** (obtained from https://ptm.asu.edu)
+
+v_vdd VDD 0 1.8
+v_gnd VSS 0 0
+.global VDD VSS
+
+*Model Description
+.param temp=27
+
+*Include model file
+.lib "/scrap/users/schiavon/gitdir/skywater-pdk/libraries/sky130_fd_pr/latest/models/sky130.lib.spice" tt
+
+*d g s b
+.SUBCKT myinverter a z VDD VSS
+X1 z a VDD VDD sky130_fd_pr__pfet_01v8 w =0.84 l = 0.15
+X2 z a VSS VSS sky130_fd_pr__nfet_01v8 w =0.36 l = 0.15
+.ENDS myinverter

hw/ip_examples/ams/data/ams.hjson

@@ -14,7 +14,7 @@
       swaccess: "rw",
       hwaccess: "hro",
       fields: [
-        { bits: "1:0", name:"VALUE", desc: "Set the ADC threshold value" }
+        { bits: "0", name:"VALUE", desc: "Set the ADC threshold value" }
       ]
     },
     { name:     "GET",

hw/ip_examples/ams/rtl/ams.sv

@@ -19,9 +19,9 @@ module ams #(
 
   assign hw2reg.get.de = 1;
 
-  ams_adc_1b ams_adc_1b_i (
-      .sel(reg2hw.sel.q),
-      .out(hw2reg.get.d)
+  myinverter myinverter_i (
+      .a(reg2hw.sel.q),
+      .z(hw2reg.get.d)
   );
 
   ams_reg_top #(

hw/ip_examples/ams/rtl/ams_reg_pkg.sv

@@ -13,7 +13,7 @@ package ams_reg_pkg;
   // Typedefs for registers //
   ////////////////////////////
 
-  typedef struct packed {logic [1:0] q;} ams_reg2hw_sel_reg_t;
+  typedef struct packed {logic q;} ams_reg2hw_sel_reg_t;
 
   typedef struct packed {logic q;} ams_reg2hw_get_reg_t;
 
@@ -24,7 +24,7 @@ package ams_reg_pkg;
 
   // Register -> HW type
   typedef struct packed {
-    ams_reg2hw_sel_reg_t sel;  // [2:1]
+    ams_reg2hw_sel_reg_t sel;  // [1:1]
     ams_reg2hw_get_reg_t get;  // [0:0]
   } ams_reg2hw_t;
 

hw/ip_examples/ams/rtl/ams_reg_top.sv

@@ -68,18 +68,18 @@ module ams_reg_top #(
   // Define SW related signals
   // Format: <reg>_<field>_{wd|we|qs}
   //        or <reg>_{wd|we|qs} if field == 1 or 0
-  logic [1:0] sel_qs;
-  logic [1:0] sel_wd;
+  logic sel_qs;
+  logic sel_wd;
   logic sel_we;
   logic get_qs;
 
   // Register instances
   // R[sel]: V(False)
 
   prim_subreg #(
-      .DW      (2),
+      .DW      (1),
       .SWACCESS("RW"),
-      .RESVAL  (2'h0)
+      .RESVAL  (1'h0)
   ) u_sel (
       .clk_i (clk_i),
       .rst_ni(rst_ni),
@@ -146,14 +146,14 @@ module ams_reg_top #(
   end
 
   assign sel_we = addr_hit[0] & reg_we & !reg_error;
-  assign sel_wd = reg_wdata[1:0];
+  assign sel_wd = reg_wdata[0];
 
   // Read data return
   always_comb begin
     reg_rdata_next = '0;
     unique case (1'b1)
       addr_hit[0]: begin
-        reg_rdata_next[1:0] = sel_qs;
+        reg_rdata_next[0] = sel_qs;
       end
 
       addr_hit[1]: begin

hw/ip_examples/ams/rtl/dummy_adc.sv → hw/ip_examples/ams/rtl/dummy_myinverter.sv

@@ -2,10 +2,10 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-module ams_adc_1b (
-    input logic [1:0] sel,
-    output logic out
+module myinverter (
+    input  logic a,
+    output logic z
 );
 
-endmodule : ams_adc_1b
+endmodule : myinverter