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[sw] add memory regions headers (core_v_mini_mcu_memory.h) #576

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Aug 10, 2024
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[sw] add memory regions headers (core_v_mini_mcu_memory.h) #576

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1 change: 1 addition & 0 deletions .gitignore
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Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,7 @@ hw/fpga/scripts/generate_sram.tcl
# same for the C header file and linker scripts and assembly files
sw/device/lib/crt/crt0.S
sw/device/lib/runtime/core_v_mini_mcu.h
sw/device/lib/runtime/core_v_mini_mcu_memory.h
sw/linker/link.ld
sw/linker/link_flash_exec.ld
sw/linker/link_flash_load.ld
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1 change: 1 addition & 0 deletions Makefile
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Expand Up @@ -113,6 +113,7 @@ mcu-gen:
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/system/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/system/x_heep_system.sv.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir sw/device/lib/runtime --cpu $(CPU) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --header-c sw/device/lib/runtime/core_v_mini_mcu.h.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir sw/device/lib/runtime --cpu $(CPU) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --header-c sw/device/lib/runtime/core_v_mini_mcu_memory.h.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir $(LINK_FOLDER) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --linker_script $(LINK_FOLDER)/link.ld.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir . --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --pkg-sv ./core-v-mini-mcu.upf.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir . --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --pkg-sv ./core-v-mini-mcu.dc.upf.tpl
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29 changes: 29 additions & 0 deletions sw/device/lib/runtime/core_v_mini_mcu_memory.h.tpl
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@@ -0,0 +1,29 @@
// Copyright 2024 EPFL
// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1

#ifndef COREV_MINI_MCU_MEMORY_H_
#define COREV_MINI_MCU_MEMORY_H_

#ifdef __cplusplus
extern "C" {
#endif // __cplusplus
#include "core_v_mini_mcu.h"
typedef struct memory_address {
unsigned int start;
unsigned int end;
} xheep_memory_address_t;

xheep_memory_address_t xheep_memory_regions[MEMORY_BANKS] = {
% for bank in xheep.iter_ram_banks():
{.start = RAM${bank.name()}_START_ADDRESS, .end = RAM${bank.name()}_END_ADDRESS},
% endfor
};

#ifdef __cplusplus
} // extern "C"
#endif // __cplusplus

#endif // COREV_MINI_MCU_MEMORY_H_
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