Erase DMA type params (#2261)

* Split PdmaChannel into two * Take &self in PDMA traits * Implement type-erased PDMA channels * Remove Degraded assoc type * Move degrade fns to base trait * Use PeripheralDmaChannel on constructors only * Remove WithDmaAes use * Erase DMA type params * Clean up examples/tests * Remove redundant trait bounds * Remove peripheral-specific DMA traits * Document i2s change * Clean up parl_io * Deduplicate InterruptAccess * Fix cfg * Implement runtime compatibility check * Clean up a bit * Document changes * Swap Channel type params, erase dma channel * Unsplit traits * Remove redundant cfg * Fix docs * Simplify DmaEligible * Remove unsafe code * Revert "Swap Channel type params, erase dma channel" This reverts commit 415e45e. * Allow different degraded DMA types * Allow converting into peripheral-specific DMA channel, use it for compat check * Erase PDMA types without AnyPdmaChannel * Hide degrade fns for now, remove from MG * Clean up SPI slave * Fix QSPI test * Fix mem2mem, fix S3 peripherals * Fix S2 * Remove AnyPdmaChannel * Remove PeripheralDmaChannel * Remove unnecessary degrade call
esp-rs · Oct 8, 2024 · 7ca1b43 · 7ca1b43
1 parent f26eef6
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diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md
@@ -66,6 +66,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Change `DmaTxBuf` to support PSRAM on `esp32s3` (#2161)
 - I2c `transaction` is now also available as a inherent function, lift size limit on `write`,`read` and `write_read` (#2262)
 - SPI transactions are now cancelled if the transfer object (or async Future) is dropped. (#2216)
+- The DMA channel types have been removed from peripherals (#2261)
 
 ### Fixed
 
@@ -108,6 +109,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Removed the `place-spi-driver-in-ram` feature, this is now enabled via [esp-config](https://docs.rs/esp-config) (#2156)
 - Removed `esp_hal::spi::slave::prelude` (#2260)
 - Removed `esp_hal::spi::slave::WithDmaSpiN` traits (#2260)
+- The `WithDmaAes` trait has been removed (#2261)
+- The `I2s::new_i2s1` constructor has been removed (#2261)
 
 ## [0.20.1] - 2024-08-30
 

diff --git a/esp-hal/MIGRATING-0.20.md b/esp-hal/MIGRATING-0.20.md
@@ -121,11 +121,17 @@ When using the asymmetric variant of the macro to create DMA buffers and descrip
 + let (_, _, tx_buffer, tx_descriptors) = dma_buffers!(0, 32000);
 ```
 
-## Removed UART constructors
+## Removed constructors
+
+### UART
 
 The `Uart::new_with_default_pins` and `Uart::new_async_with_default_pins` constructors
 have been removed. Use `new` or `new_async` instead.
 
+### I2S1
+
+The `I2s::new_i2s1` constructor has been removed. Use `I2s::new` instead.
+
 ## Timer changes
 
 ### `ErasedTimer` rename
@@ -319,3 +325,17 @@ Diff of the `psram_quad.rs` example
 ## eFuse
 
 Calling `Efuse::read_field_le::<bool>()` no longer compiles. Use `Efuse::read_bit()` instead.
+
+## DMA
+
+The DMA channel types have been removed from peripherals.
+
+A non-exhausitve list demonstrating this change:
+
+```diff
+-I2sTx<'static, I2S0, DmaChannel0, Async>
++I2sTx<'static, I2S0, Async>
+
+-SpiDma<'static, esp_hal::peripherals::SPI2, DmaChannel0, HalfDuplexMode, Blocking>
++SpiDma<'static, esp_hal::peripherals::SPI2, HalfDuplexMode, Blocking>
+```
diff --git a/esp-hal/src/aes/mod.rs b/esp-hal/src/aes/mod.rs
@@ -235,27 +235,23 @@ pub mod dma {
         aes::{Key, Mode},
         dma::{
             dma_private::{DmaSupport, DmaSupportRx, DmaSupportTx},
-            AesPeripheral,
             Channel,
             ChannelRx,
             ChannelTx,
             DescriptorChain,
-            DmaChannel,
+            DmaChannelConvert,
             DmaDescriptor,
+            DmaEligible,
             DmaPeripheral,
             DmaTransferRxTx,
             ReadBuffer,
             Rx,
             Tx,
             WriteBuffer,
         },
+        peripherals::AES,
     };
 
-    #[cfg(gdma)]
-    type DefaultChannel = crate::dma::AnyDmaChannel;
-    #[cfg(pdma)]
-    type DefaultChannel = (); // Replace with PDMA channel once support is added.
-
     const ALIGN_SIZE: usize = core::mem::size_of::<u32>();
 
     /// Specifies the block cipher modes available for AES operations.
@@ -275,69 +271,43 @@ pub mod dma {
     }
 
     /// A DMA capable AES instance.
-    pub struct AesDma<'d, C = DefaultChannel>
-    where
-        C: DmaChannel,
-        C::P: AesPeripheral,
-    {
+    pub struct AesDma<'d> {
         /// The underlying [`Aes`](super::Aes) driver
         pub aes: super::Aes<'d>,
 
-        pub(crate) channel: Channel<'d, C, crate::Blocking>,
+        channel: Channel<'d, <AES as DmaEligible>::Dma, crate::Blocking>,
         rx_chain: DescriptorChain,
         tx_chain: DescriptorChain,
     }
 
-    /// Functionality for using AES with DMA.
-    pub trait WithDmaAes<'d, C>
-    where
-        C: DmaChannel,
-        C::P: AesPeripheral,
-    {
+    impl<'d> crate::aes::Aes<'d> {
         /// Enable DMA for the current instance of the AES driver
-        fn with_dma(
-            self,
-            channel: Channel<'d, C, crate::Blocking>,
-            rx_descriptors: &'static mut [DmaDescriptor],
-            tx_descriptors: &'static mut [DmaDescriptor],
-        ) -> AesDma<'d, C>;
-    }
-
-    impl<'d, C> WithDmaAes<'d, C> for crate::aes::Aes<'d>
-    where
-        C: DmaChannel,
-        C::P: AesPeripheral,
-    {
-        fn with_dma(
+        pub fn with_dma<C>(
             self,
             channel: Channel<'d, C, crate::Blocking>,
             rx_descriptors: &'static mut [DmaDescriptor],
             tx_descriptors: &'static mut [DmaDescriptor],
-        ) -> AesDma<'d, C> {
+        ) -> AesDma<'d>
+        where
+            Self: Sized,
+            C: DmaChannelConvert<<AES as DmaEligible>::Dma>,
+        {
             AesDma {
                 aes: self,
-                channel,
+                channel: channel.degrade(),
                 rx_chain: DescriptorChain::new(rx_descriptors),
                 tx_chain: DescriptorChain::new(tx_descriptors),
             }
         }
     }
 
-    impl<'d, C> core::fmt::Debug for AesDma<'d, C>
-    where
-        C: DmaChannel,
-        C::P: AesPeripheral,
-    {
+    impl<'d> core::fmt::Debug for AesDma<'d> {
         fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
             f.debug_struct("AesDma").finish()
         }
     }
 
-    impl<'d, C> DmaSupport for AesDma<'d, C>
-    where
-        C: DmaChannel,
-        C::P: AesPeripheral,
-    {
+    impl<'d> DmaSupport for AesDma<'d> {
         fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) {
             while self.aes.aes.state().read().state().bits() != 2 // DMA status DONE == 2
             && !self.channel.tx.is_done()
@@ -353,12 +323,8 @@ pub mod dma {
         }
     }
 
-    impl<'d, C> DmaSupportTx for AesDma<'d, C>
-    where
-        C: DmaChannel,
-        C::P: AesPeripheral,
-    {
-        type TX = ChannelTx<'d, C>;
+    impl<'d> DmaSupportTx for AesDma<'d> {
+        type TX = ChannelTx<'d, <AES as DmaEligible>::Dma>;
 
         fn tx(&mut self) -> &mut Self::TX {
             &mut self.channel.tx
@@ -369,12 +335,8 @@ pub mod dma {
         }
     }
 
-    impl<'d, C> DmaSupportRx for AesDma<'d, C>
-    where
-        C: DmaChannel,
-        C::P: AesPeripheral,
-    {
-        type RX = ChannelRx<'d, C>;
+    impl<'d> DmaSupportRx for AesDma<'d> {
+        type RX = ChannelRx<'d, <AES as DmaEligible>::Dma>;
 
         fn rx(&mut self) -> &mut Self::RX {
             &mut self.channel.rx
@@ -385,11 +347,7 @@ pub mod dma {
         }
     }
 
-    impl<'d, C> AesDma<'d, C>
-    where
-        C: DmaChannel,
-        C::P: AesPeripheral,
-    {
+    impl<'d> AesDma<'d> {
         /// Writes the encryption key to the AES hardware, checking that its
         /// length matches expected constraints.
         pub fn write_key<K>(&mut self, key: K)