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Regenerate all PACs using [email protected]
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@jessebraham
jessebraham committed Nov 7, 2024
1 parent 677351b commit 8c6dba3
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1 change: 0 additions & 1 deletion esp32/src/aes/endian.rs
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Expand Up @@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:1 - Endianness selection register. See Table 22-2 for details."]
#[inline(always)]
#[must_use]
pub fn endian(&mut self) -> ENDIAN_W<ENDIAN_SPEC> {
ENDIAN_W::new(self, 0)
}
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1 change: 0 additions & 1 deletion esp32/src/aes/key.rs
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Expand Up @@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:7 - AES key material register."]
#[inline(always)]
#[must_use]
pub fn key(&mut self) -> KEY_W<KEY_SPEC> {
KEY_W::new(self, 0)
}
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1 change: 0 additions & 1 deletion esp32/src/aes/mode.rs
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Expand Up @@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:7 - Selects the AES accelerator mode of operation. See Table 22-1 for details."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> MODE_W<MODE_SPEC> {
MODE_W::new(self, 0)
}
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1 change: 0 additions & 1 deletion esp32/src/aes/start.rs
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Expand Up @@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<START_SPEC> {
impl W {
#[doc = "Bit 0 - Write 1 to start the AES operation."]
#[inline(always)]
#[must_use]
pub fn start(&mut self) -> START_W<START_SPEC> {
START_W::new(self, 0)
}
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1 change: 0 additions & 1 deletion esp32/src/aes/text.rs
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Expand Up @@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:7 - Plaintext and ciphertext register."]
#[inline(always)]
#[must_use]
pub fn text(&mut self) -> TEXT_W<TEXT_SPEC> {
TEXT_W::new(self, 0)
}
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4 changes: 4 additions & 0 deletions esp32/src/apb_ctrl.rs
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Expand Up @@ -52,6 +52,8 @@ impl RegisterBlock {
&self.apb_saradc_fsm
}
#[doc = "0x1c..0x2c - "]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `APB_SARADC_SAR1_PATT_TAB1` register.</div>"]
#[inline(always)]
pub const fn apb_saradc_sar1_patt_tab(&self, n: usize) -> &APB_SARADC_SAR1_PATT_TAB {
&self.apb_saradc_sar1_patt_tab[n]
Expand Down Expand Up @@ -83,6 +85,8 @@ impl RegisterBlock {
self.apb_saradc_sar1_patt_tab(3)
}
#[doc = "0x2c..0x3c - "]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `APB_SARADC_SAR2_PATT_TAB1` register.</div>"]
#[inline(always)]
pub const fn apb_saradc_sar2_patt_tab(&self, n: usize) -> &APB_SARADC_SAR2_PATT_TAB {
&self.apb_saradc_sar2_patt_tab[n]
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13 changes: 0 additions & 13 deletions esp32/src/apb_ctrl/apb_saradc_ctrl.rs
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Expand Up @@ -144,79 +144,66 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn saradc_start_force(&mut self) -> SARADC_START_FORCE_W<APB_SARADC_CTRL_SPEC> {
SARADC_START_FORCE_W::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn saradc_start(&mut self) -> SARADC_START_W<APB_SARADC_CTRL_SPEC> {
SARADC_START_W::new(self, 1)
}
#[doc = "Bit 2 - 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL"]
#[inline(always)]
#[must_use]
pub fn saradc_sar2_mux(&mut self) -> SARADC_SAR2_MUX_W<APB_SARADC_CTRL_SPEC> {
SARADC_SAR2_MUX_W::new(self, 2)
}
#[doc = "Bits 3:4 - 0: single mode 1: double mode 2: alternate mode"]
#[inline(always)]
#[must_use]
pub fn saradc_work_mode(&mut self) -> SARADC_WORK_MODE_W<APB_SARADC_CTRL_SPEC> {
SARADC_WORK_MODE_W::new(self, 3)
}
#[doc = "Bit 5 - 0: SAR1 1: SAR2 only work for single SAR mode"]
#[inline(always)]
#[must_use]
pub fn saradc_sar_sel(&mut self) -> SARADC_SAR_SEL_W<APB_SARADC_CTRL_SPEC> {
SARADC_SAR_SEL_W::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn saradc_sar_clk_gated(&mut self) -> SARADC_SAR_CLK_GATED_W<APB_SARADC_CTRL_SPEC> {
SARADC_SAR_CLK_GATED_W::new(self, 6)
}
#[doc = "Bits 7:14 - SAR clock divider"]
#[inline(always)]
#[must_use]
pub fn saradc_sar_clk_div(&mut self) -> SARADC_SAR_CLK_DIV_W<APB_SARADC_CTRL_SPEC> {
SARADC_SAR_CLK_DIV_W::new(self, 7)
}
#[doc = "Bits 15:18 - 0 ~ 15 means length 1 ~ 16"]
#[inline(always)]
#[must_use]
pub fn saradc_sar1_patt_len(&mut self) -> SARADC_SAR1_PATT_LEN_W<APB_SARADC_CTRL_SPEC> {
SARADC_SAR1_PATT_LEN_W::new(self, 15)
}
#[doc = "Bits 19:22 - 0 ~ 15 means length 1 ~ 16"]
#[inline(always)]
#[must_use]
pub fn saradc_sar2_patt_len(&mut self) -> SARADC_SAR2_PATT_LEN_W<APB_SARADC_CTRL_SPEC> {
SARADC_SAR2_PATT_LEN_W::new(self, 19)
}
#[doc = "Bit 23 - clear the pointer of pattern table for DIG ADC1 CTRL"]
#[inline(always)]
#[must_use]
pub fn saradc_sar1_patt_p_clear(&mut self) -> SARADC_SAR1_PATT_P_CLEAR_W<APB_SARADC_CTRL_SPEC> {
SARADC_SAR1_PATT_P_CLEAR_W::new(self, 23)
}
#[doc = "Bit 24 - clear the pointer of pattern table for DIG ADC2 CTRL"]
#[inline(always)]
#[must_use]
pub fn saradc_sar2_patt_p_clear(&mut self) -> SARADC_SAR2_PATT_P_CLEAR_W<APB_SARADC_CTRL_SPEC> {
SARADC_SAR2_PATT_P_CLEAR_W::new(self, 24)
}
#[doc = "Bit 25 - 1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits."]
#[inline(always)]
#[must_use]
pub fn saradc_data_sar_sel(&mut self) -> SARADC_DATA_SAR_SEL_W<APB_SARADC_CTRL_SPEC> {
SARADC_DATA_SAR_SEL_W::new(self, 25)
}
#[doc = "Bit 26 - 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix"]
#[inline(always)]
#[must_use]
pub fn saradc_data_to_i2s(&mut self) -> SARADC_DATA_TO_I2S_W<APB_SARADC_CTRL_SPEC> {
SARADC_DATA_TO_I2S_W::new(self, 26)
}
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4 changes: 0 additions & 4 deletions esp32/src/apb_ctrl/apb_saradc_ctrl2.rs
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Expand Up @@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn saradc_meas_num_limit(&mut self) -> SARADC_MEAS_NUM_LIMIT_W<APB_SARADC_CTRL2_SPEC> {
SARADC_MEAS_NUM_LIMIT_W::new(self, 0)
}
#[doc = "Bits 1:8 - max conversion number"]
#[inline(always)]
#[must_use]
pub fn saradc_max_meas_num(&mut self) -> SARADC_MAX_MEAS_NUM_W<APB_SARADC_CTRL2_SPEC> {
SARADC_MAX_MEAS_NUM_W::new(self, 1)
}
#[doc = "Bit 9 - 1: data to DIG ADC1 CTRL is inverted otherwise not"]
#[inline(always)]
#[must_use]
pub fn saradc_sar1_inv(&mut self) -> SARADC_SAR1_INV_W<APB_SARADC_CTRL2_SPEC> {
SARADC_SAR1_INV_W::new(self, 9)
}
#[doc = "Bit 10 - 1: data to DIG ADC2 CTRL is inverted otherwise not"]
#[inline(always)]
#[must_use]
pub fn saradc_sar2_inv(&mut self) -> SARADC_SAR2_INV_W<APB_SARADC_CTRL2_SPEC> {
SARADC_SAR2_INV_W::new(self, 10)
}
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4 changes: 0 additions & 4 deletions esp32/src/apb_ctrl/apb_saradc_fsm.rs
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Expand Up @@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn saradc_rstb_wait(&mut self) -> SARADC_RSTB_WAIT_W<APB_SARADC_FSM_SPEC> {
SARADC_RSTB_WAIT_W::new(self, 0)
}
#[doc = "Bits 8:15"]
#[inline(always)]
#[must_use]
pub fn saradc_standby_wait(&mut self) -> SARADC_STANDBY_WAIT_W<APB_SARADC_FSM_SPEC> {
SARADC_STANDBY_WAIT_W::new(self, 8)
}
#[doc = "Bits 16:23"]
#[inline(always)]
#[must_use]
pub fn saradc_start_wait(&mut self) -> SARADC_START_WAIT_W<APB_SARADC_FSM_SPEC> {
SARADC_START_WAIT_W::new(self, 16)
}
#[doc = "Bits 24:31 - sample cycles"]
#[inline(always)]
#[must_use]
pub fn saradc_sample_cycle(&mut self) -> SARADC_SAMPLE_CYCLE_W<APB_SARADC_FSM_SPEC> {
SARADC_SAMPLE_CYCLE_W::new(self, 24)
}
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1 change: 0 additions & 1 deletion esp32/src/apb_ctrl/apb_saradc_sar1_patt_tab.rs
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Expand Up @@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:31 - item 0 ~ 3 for pattern table 1 (each item one byte)"]
#[inline(always)]
#[must_use]
pub fn saradc_sar1_patt_tab1(
&mut self,
) -> SARADC_SAR1_PATT_TAB1_W<APB_SARADC_SAR1_PATT_TAB_SPEC> {
Expand Down
1 change: 0 additions & 1 deletion esp32/src/apb_ctrl/apb_saradc_sar2_patt_tab.rs
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Expand Up @@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:31 - item 0 ~ 3 for pattern table 2 (each item one byte)"]
#[inline(always)]
#[must_use]
pub fn saradc_sar2_patt_tab1(
&mut self,
) -> SARADC_SAR2_PATT_TAB1_W<APB_SARADC_SAR2_PATT_TAB_SPEC> {
Expand Down
1 change: 0 additions & 1 deletion esp32/src/apb_ctrl/apll_tick_conf.rs
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Expand Up @@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn apll_tick_num(&mut self) -> APLL_TICK_NUM_W<APLL_TICK_CONF_SPEC> {
APLL_TICK_NUM_W::new(self, 0)
}
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1 change: 0 additions & 1 deletion esp32/src/apb_ctrl/ck8m_tick_conf.rs
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Expand Up @@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn ck8m_tick_num(&mut self) -> CK8M_TICK_NUM_W<CK8M_TICK_CONF_SPEC> {
CK8M_TICK_NUM_W::new(self, 0)
}
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1 change: 0 additions & 1 deletion esp32/src/apb_ctrl/date.rs
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Expand Up @@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
DATE_W::new(self, 0)
}
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1 change: 0 additions & 1 deletion esp32/src/apb_ctrl/pll_tick_conf.rs
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Expand Up @@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn pll_tick_num(&mut self) -> PLL_TICK_NUM_W<PLL_TICK_CONF_SPEC> {
PLL_TICK_NUM_W::new(self, 0)
}
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5 changes: 0 additions & 5 deletions esp32/src/apb_ctrl/sysclk_conf.rs
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Expand Up @@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:9"]
#[inline(always)]
#[must_use]
pub fn pre_div_cnt(&mut self) -> PRE_DIV_CNT_W<SYSCLK_CONF_SPEC> {
PRE_DIV_CNT_W::new(self, 0)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn clk_320m_en(&mut self) -> CLK_320M_EN_W<SYSCLK_CONF_SPEC> {
CLK_320M_EN_W::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn clk_en(&mut self) -> CLK_EN_W<SYSCLK_CONF_SPEC> {
CLK_EN_W::new(self, 11)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn rst_tick_cnt(&mut self) -> RST_TICK_CNT_W<SYSCLK_CONF_SPEC> {
RST_TICK_CNT_W::new(self, 12)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn quick_clk_chng(&mut self) -> QUICK_CLK_CHNG_W<SYSCLK_CONF_SPEC> {
QUICK_CLK_CHNG_W::new(self, 13)
}
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1 change: 0 additions & 1 deletion esp32/src/apb_ctrl/xtal_tick_conf.rs
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Expand Up @@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn xtal_tick_num(&mut self) -> XTAL_TICK_NUM_W<XTAL_TICK_CONF_SPEC> {
XTAL_TICK_NUM_W::new(self, 0)
}
Expand Down
4 changes: 0 additions & 4 deletions esp32/src/bb/bbpd_ctrl.rs
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Expand Up @@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn dc_est_force_pd(&mut self) -> DC_EST_FORCE_PD_W<BBPD_CTRL_SPEC> {
DC_EST_FORCE_PD_W::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn dc_est_force_pu(&mut self) -> DC_EST_FORCE_PU_W<BBPD_CTRL_SPEC> {
DC_EST_FORCE_PU_W::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn fft_force_pd(&mut self) -> FFT_FORCE_PD_W<BBPD_CTRL_SPEC> {
FFT_FORCE_PD_W::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn fft_force_pu(&mut self) -> FFT_FORCE_PU_W<BBPD_CTRL_SPEC> {
FFT_FORCE_PU_W::new(self, 3)
}
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6 changes: 0 additions & 6 deletions esp32/src/dport/ahb_lite_mask.rs
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Expand Up @@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pro(&mut self) -> PRO_W<AHB_LITE_MASK_SPEC> {
PRO_W::new(self, 0)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn app(&mut self) -> APP_W<AHB_LITE_MASK_SPEC> {
APP_W::new(self, 4)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn sdio(&mut self) -> SDIO_W<AHB_LITE_MASK_SPEC> {
SDIO_W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn prodport(&mut self) -> PRODPORT_W<AHB_LITE_MASK_SPEC> {
PRODPORT_W::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn appdport(&mut self) -> APPDPORT_W<AHB_LITE_MASK_SPEC> {
APPDPORT_W::new(self, 10)
}
#[doc = "Bits 11:13"]
#[inline(always)]
#[must_use]
pub fn ahb_lite_sdhost_pid(&mut self) -> AHB_LITE_SDHOST_PID_W<AHB_LITE_MASK_SPEC> {
AHB_LITE_SDHOST_PID_W::new(self, 11)
}
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1 change: 0 additions & 1 deletion esp32/src/dport/ahb_mpu_table_0.rs
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Expand Up @@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn ahb_access_grant_0(&mut self) -> AHB_ACCESS_GRANT_0_W<AHB_MPU_TABLE_0_SPEC> {
AHB_ACCESS_GRANT_0_W::new(self, 0)
}
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1 change: 0 additions & 1 deletion esp32/src/dport/ahb_mpu_table_1.rs
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Expand Up @@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:8"]
#[inline(always)]
#[must_use]
pub fn ahb_access_grant_1(&mut self) -> AHB_ACCESS_GRANT_1_W<AHB_MPU_TABLE_1_SPEC> {
AHB_ACCESS_GRANT_1_W::new(self, 0)
}
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1 change: 0 additions & 1 deletion esp32/src/dport/ahblite_mpu_table_apb_ctrl.rs
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Expand Up @@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn apbctrl_access_grant_config(
&mut self,
) -> APBCTRL_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_APB_CTRL_SPEC> {
Expand Down
1 change: 0 additions & 1 deletion esp32/src/dport/ahblite_mpu_table_bb.rs
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Expand Up @@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn bb_access_grant_config(
&mut self,
) -> BB_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_BB_SPEC> {
Expand Down
1 change: 0 additions & 1 deletion esp32/src/dport/ahblite_mpu_table_bt.rs
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Expand Up @@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn bt_access_grant_config(
&mut self,
) -> BT_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_BT_SPEC> {
Expand Down
1 change: 0 additions & 1 deletion esp32/src/dport/ahblite_mpu_table_bt_buffer.rs
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Expand Up @@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn btbuffer_access_grant_config(
&mut self,
) -> BTBUFFER_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_BT_BUFFER_SPEC> {
Expand Down
1 change: 0 additions & 1 deletion esp32/src/dport/ahblite_mpu_table_btmac.rs
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Expand Up @@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn btmac_access_grant_config(
&mut self,
) -> BTMAC_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_BTMAC_SPEC> {
Expand Down
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