esp-rs · jessebraham · Mar 5, 2024 · Mar 5, 2024 · Mar 5, 2024
diff --git a/.github/actions/check/action.yml b/.github/actions/check/action.yml
@@ -18,12 +18,6 @@ runs:
   using: composite
 
   steps:
-    # If using the 'esp' toolchain, we also need to have 'nightly' installed
-    # prior to invoking the 'xtensa-toolchain' action:
-
-    - uses: dtolnay/rust-toolchain@nightly
-      if: startsWith(inputs.target, 'xtensa')
-
     # Install the newest available version of the specified toolchain,
     # required for building the PAC:
 
@@ -43,13 +37,13 @@ runs:
     # Build the PAC using the newest available version of the specified
     # toolchain:
 
-    - name: Build PAC
+    - name: Build (${{ inputs.package }})
       shell: bash
-      run: cd ${{ inputs.package }} && cargo check --all-targets
+      run: cd ${{ inputs.package }} && cargo check
 
     # Install the MSRV of the specified toolchain:
 
-    - uses: dtolnay/rust-toolchain@master
+    - uses: dtolnay/rust-toolchain@v1
       if: startsWith(inputs.target, 'riscv')
       with:
         toolchain: ${{ inputs.msrv }}
@@ -70,9 +64,9 @@ runs:
     - name: Check MSRV
       if: startsWith(inputs.target, 'riscv')
       shell: bash
-      run: cd ${{ inputs.package }} && cargo +${{ inputs.msrv }} check --all-targets
+      run: cd ${{ inputs.package }} && cargo +${{ inputs.msrv }} check
 
     - name: Check MSRV
       if: startsWith(inputs.target, 'xtensa')
       shell: bash
-      run: cd ${{ inputs.package }} && cargo check --all-targets
+      run: cd ${{ inputs.package }} && cargo check
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -39,8 +39,7 @@ jobs:
             { package: "esp32c3", target: "riscv32imc-unknown-none-elf" },
             { package: "esp32c6", target: "riscv32imac-unknown-none-elf" },
             { package: "esp32h2", target: "riscv32imac-unknown-none-elf" },
-            # FIXME: actual target is `riscv32imafc-unknown-none-elf`
-            { package: "esp32p4", target: "riscv32imac-unknown-none-elf" },
+            { package: "esp32p4", target: "riscv32imafc-unknown-none-elf" },
 
             # RISC-V (Ultra) Low-Power:
             { package: "esp32c6-lp",  target: "riscv32imac-unknown-none-elf" },
@@ -49,9 +48,9 @@ jobs:
           ]
 
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
       - uses: ./.github/actions/check
         with:
-          msrv: "1.67.0"
+          msrv: "1.76.0"
           package: ${{ matrix.build.package }}
           target: ${{ matrix.build.target }}
diff --git a/README.md b/README.md
@@ -92,7 +92,7 @@ Prior to opening a pull request, we ask that you please:
 
 ## MSRV
 
-The **M**inimum **S**upported **R**ust **V**ersion is `1.67.0` for all packages.
+The **M**inimum **S**upported **R**ust **V**ersion is `1.76.0` for all packages.
 
 Note that targeting the Xtensa ISA currently requires the use of the [esp-rs/rust] compiler fork, which can be installed using [esp-rs/espup].
 

diff --git a/esp32/Cargo.toml b/esp32/Cargo.toml
@@ -2,7 +2,7 @@
 name = "esp32"
 version = "0.29.0"
 edition = "2021"
-rust-version = "1.67"
+rust-version = "1.76"
 description = "Peripheral access crate for the ESP32"
 repository = "https://github.com/esp-rs/esp-pacs"
 license = "MIT OR Apache-2.0"

diff --git a/esp32c2/Cargo.toml b/esp32c2/Cargo.toml
@@ -2,7 +2,7 @@
 name = "esp32c2"
 version = "0.18.0"
 edition = "2021"
-rust-version = "1.67"
+rust-version = "1.76"
 description = "Peripheral access crate for the ESP32-C2"
 repository = "https://github.com/esp-rs/esp-pacs"
 license = "MIT OR Apache-2.0"

diff --git a/esp32c3/Cargo.toml b/esp32c3/Cargo.toml
@@ -2,7 +2,7 @@
 name = "esp32c3"
 version = "0.21.0"
 edition = "2021"
-rust-version = "1.67"
+rust-version = "1.76"
 description = "Peripheral access crate for the ESP32-C3"
 repository = "https://github.com/esp-rs/esp-pacs"
 license = "MIT OR Apache-2.0"

diff --git a/esp32c6-lp/Cargo.toml b/esp32c6-lp/Cargo.toml
@@ -2,7 +2,7 @@
 name = "esp32c6-lp"
 version = "0.1.0"
 edition = "2021"
-rust-version = "1.67"
+rust-version = "1.76"
 description = "Peripheral access crate for the ESP32-C6's LP coprocessor"
 repository = "https://github.com/esp-rs/esp-pacs"
 license = "MIT OR Apache-2.0"

diff --git a/esp32c6/Cargo.toml b/esp32c6/Cargo.toml
@@ -2,7 +2,7 @@
 name = "esp32c6"
 version = "0.12.0"
 edition = "2021"
-rust-version = "1.67"
+rust-version = "1.76"
 description = "Peripheral access crate for the ESP32-C6"
 repository = "https://github.com/esp-rs/esp-pacs"
 license = "MIT OR Apache-2.0"

diff --git a/esp32h2/Cargo.toml b/esp32h2/Cargo.toml
@@ -2,7 +2,7 @@
 name = "esp32h2"
 version = "0.8.0"
 edition = "2021"
-rust-version = "1.67"
+rust-version = "1.76"
 description = "Peripheral access crate for the ESP32-H2"
 repository = "https://github.com/esp-rs/esp-pacs"
 license = "MIT OR Apache-2.0"

diff --git a/esp32p4/.cargo/config.toml b/esp32p4/.cargo/config.toml
@@ -1,6 +1,5 @@
 [build]
-# FIXME: actual target is `riscv32imafc-unknown-none-elf`
-target = "riscv32imac-unknown-none-elf"
+target = "riscv32imafc-unknown-none-elf"
 
 [unstable]
 build-std = ["core"]
diff --git a/esp32p4/Cargo.toml b/esp32p4/Cargo.toml
@@ -2,7 +2,7 @@
 name = "esp32p4"
 version = "0.1.0"
 edition = "2021"
-rust-version = "1.67"
+rust-version = "1.76"
 description = "Peripheral access crate for the ESP32-P4"
 repository = "https://github.com/esp-rs/esp-pacs"
 license = "MIT OR Apache-2.0"

diff --git a/esp32s2-ulp/Cargo.toml b/esp32s2-ulp/Cargo.toml
@@ -2,7 +2,7 @@
 name = "esp32s2-ulp"
 version = "0.1.0"
 edition = "2021"
-rust-version = "1.67"
+rust-version = "1.76"
 description = "Peripheral access crate for the ESP32-S2's RISC-V ULP coprocessor"
 repository = "https://github.com/esp-rs/esp-pacs"
 license = "MIT OR Apache-2.0"

diff --git a/esp32s2/Cargo.toml b/esp32s2/Cargo.toml
@@ -2,7 +2,7 @@
 name = "esp32s2"
 version = "0.20.0"
 edition = "2021"
-rust-version = "1.67"
+rust-version = "1.76"
 description = "Peripheral access crate for the ESP32-S2"
 repository = "https://github.com/esp-rs/esp-pacs"
 license = "MIT OR Apache-2.0"

diff --git a/esp32s3-ulp/Cargo.toml b/esp32s3-ulp/Cargo.toml
@@ -2,7 +2,7 @@
 name = "esp32s3-ulp"
 version = "0.1.0"
 edition = "2021"
-rust-version = "1.67"
+rust-version = "1.76"
 description = "Peripheral access crate for the ESP32-S3's RISC-V ULP coprocessor"
 repository = "https://github.com/esp-rs/esp-pacs"
 license = "MIT OR Apache-2.0"

diff --git a/esp32s3/Cargo.toml b/esp32s3/Cargo.toml
@@ -2,7 +2,7 @@
 name = "esp32s3"
 version = "0.24.0"
 edition = "2021"
-rust-version = "1.67"
+rust-version = "1.76"
 description = "Peripheral access crate for the ESP32-S3"
 repository = "https://github.com/esp-rs/esp-pacs"
 license = "MIT OR Apache-2.0"
-Original file line number
+Diff line change
@@ Expand Up / @@ -92,7 +92,7 @@ Prior to opening a pull request, we ask that you please: @@
     ## MSRV
-    The **M**inimum **S**upported **R**ust **V**ersion is `1.67.0` for all packages.
+    The **M**inimum **S**upported **R**ust **V**ersion is `1.76.0` for all packages.
     Note that targeting the Xtensa ISA currently requires the use of the [esp-rs/rust] compiler fork, which can be installed using [esp-rs/espup].
@@ Expand Down @@