Fix inline assembly test

[taiki-e]

Depends on #240. (The first commit is from it.)

inline assembly test (tests/assembly/asm/xtensa-types.rs) is currently broken due to some issues. This PR fixes them:

• feature(asm_experimental_arch) is required to use inline assembly.
• "CHECK-LABEL:" for a5_i32 is wrong (typo)
• reg tests use mov assembler macro that using or instruction. The assembler emits or, but "CHECK:" uses mov.
  • This PR fixes "CHECK:", but we might actually want to use mov.n (narrow move) instruction instead of mov.
• freg tests are broken due to an issue will be fixed by Add XTENSA_ALLOWED_FEATURES to supported_target_features #240.

[taiki-e]

Btw, this test actually appears to be doing what the ISA says it should not do.
Xtensa Instruction Set Architecture (ISA) Reference Manual (436 page) says:

ar and as should not specify the same register due to the MOV.N restriction.

[MabezDev]

Interestingly the official ISA from cadence omits this line: https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/silicon-solutions/compute-ip/isa-summary.pdf (page 495). I'll ask the LLVM team what their reference is.

[taiki-e]

Ah, it seems that what I was looking at was an old manual.

https://web.archive.org/web/20241005102231/https://0x04.net/~mwk/doc/xtensa.pdf (page 2)

Issue Date: 4/2010
RC-2010.1 Release
PD-09-0801-10-01

https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/silicon-solutions/compute-ip/isa-summary.pdf (page 2)

Product Release:RI-2021.8
Last Updated:04/2022
Modification: 737871

[MabezDev]

Thanks for the PRs! I've rolled your changes into the current Xtensa asm commit and added you as a co-author so you still get the credit. I've started the 1.82.0.2 release, I'll ping you wen the builds are complete and you can try it out before I set it to latest.

[MabezDev]

Some of the builds are starting to finish: https://github.com/esp-rs/rust-build/releases/tag/v1.82.0.2

You can install manually with espup install --toolchain-version 1.82.0.2, or you can specify it on the Xtensa GHA like this PR did esp-rs/esp-hal#2414

Let me know if you run into any issues :)