Add option to prioritize DRAM allocation over IRAM (GIT8266O-786)

[rechrtb]

If CONFIG_HEAP_DISABLE_IRAM is disabled, IRAM is the first heap region set.

ESP8266_RTOS_SDK/components/heap/port/esp8266/esp_heap_init.c

Lines 37 to 60 in d48c4c1

	void heap_caps_init(void)
	{
	extern char _bss_end;
	size_t heap_region_num = 0;
	#ifndef CONFIG_HEAP_DISABLE_IRAM
	extern char _iram_end;
	const size_t iram_size = 0x40100000 + CONFIG_SOC_IRAM_SIZE - ((size_t)&_iram_end);
	if (iram_size > HEAP_REGION_IRAM_MIN && iram_size < HEAP_REGION_IRAM_MAX) {
	g_heap_region[heap_region_num].start_addr = (uint8_t *)&_iram_end;
	g_heap_region[heap_region_num].total_size = iram_size;
	g_heap_region[heap_region_num].caps = MALLOC_CAP_32BIT | MALLOC_CAP_EXEC;
	heap_region_num++;
	}
	#endif
	g_heap_region[heap_region_num].start_addr = (uint8_t *)&_bss_end;
	g_heap_region[heap_region_num].total_size = ((size_t)(0x40000000 - (uint32_t)&_bss_end));
	g_heap_region[heap_region_num].caps = MALLOC_CAP_8BIT | MALLOC_CAP_32BIT | MALLOC_CAP_DMA;
	heap_region_num++;
	esp_heap_caps_init_region(g_heap_region, heap_region_num);
	}

The allocator, therefore, sees the IRAM region first and allocates from it when given MALLOC_CAP_32BIT.

ESP8266_RTOS_SDK/components/heap/src/esp_heap_caps.c

Lines 114 to 123 in d48c4c1

	for (num = 0; num < g_heap_region_num; num++) {
	bool trace;
	size_t head_size;
	if ((g_heap_region[num].caps & caps) != caps) {
	ESP_EARLY_LOGV(TAG, "caps in %x, num %d region %x @ %p", caps, num, g_heap_region[num].caps, &g_heap_region[num]);
	continue;
	}

This seems to incur a performance penalty given the needed unaligned access handling. This PR adds an option to set DRAM region ahead of IRAM during initialization

[CLAassistant]

All committers have signed the CLA.