espressif · woshiokteng · Jun 17, 2019 · Jun 18, 2019 · Jul 2, 2019 · Jul 2, 2019
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -42,7 +42,7 @@ build_ssc:
     - git clone $GITLAB_SSH_SERVER/yinling/SSC.git
     - cd SSC
     # try checkout same branch
-    - git checkout "${CI_BUILD_REF_NAME}_8266" || echo "Using default branch..."
+    - git checkout release/v3.2_8266 || echo "Using default branch..."
     - ./gen_misc_rtos.sh
 
 push_master_to_github:

diff --git a/SUPPORT_POLICY_CN.md b/SUPPORT_POLICY_CN.md
@@ -0,0 +1,54 @@
+有关 ESP8266 RTOS SDK 的最新支持政策，详见 [支持期限政策](./SUPPORT_POLICY_CN.md)。
+支持期限政策
+=================
+
+* [English Version](./SUPPORT_POLICY_EN.md)
+
+ESP8266 RTOS SDK 的每个主要版本和次要版本（如 V3.0、V3.1 等）自其首次稳定版本发布之日起将维护 18 个月。
+
+维护意味着 ESP8266 RTOS SDK 团队将会对 GitHub 上的发布分支继续进行 bug 修复、安全修补等，并根据需求定期发布新的 bugfix 版本。
+
+在某一版本支持期限结束，停止更新维护 (EOL) 前，建议用户升级到较新的 ESP8266 RTOS SDK 版本。根据《支持期限政策》，我们将停止对 EOL 版本进行 bug 修复。
+
+《支持期限政策》不适用于预发布版本（包括 beta、preview、`-rc` 和 `-dev` 版本等）。有时，在发布的版本中存在被标记为 "Preview" 的特定功能，则该功能也不在支持期限内。
+
+长期支持版本
+------------
+
+有些发布版本（例如 ESP8266 RTOS SDK V3.1）属于长期支持 (LTS) 版本。LTS 版本将自其首次稳定版本发布之日起维护 30 个月（2.5 年）。
+
+关于长期维护版本，在 github 上面正式的`第１次`发布该版本 release 的时候，会在标题上额外标注 `(LTS)`，例如：
+
+```
+ESP8266 RTOS SDK Release v3.4 (LTS)
+```
+
+后续的维护版本不会再额外标注 `(LTS)`，例如：
+
+```
+ESP8266 RTOS SDK Release v3.4.1
+```
+
+示例
+-----
+
+ESP8266 RTOS SDK V3.1 于 2019 年 01 月发布，属于 LTS 版本，自正式发布日开始将维护 30 个月至 2021 年 07 月停止。
+
+- V3.1 的首个发布版本为 2019 年 01 月发布的 `v3.1`。
+- ESP8266 RTOS SDK 团队将持续进行 bug 修复、安全修补等更新，并 backport 至分支 `release/v3.1`。
+- 定期从 release 分支创建稳定的 bugfix 版本，比如，`v3.1.1`、`v3.1.2` 等，并建议用户保持使用最新的 bugfix 版本。
+- V3.1 的 bugfix 版本发布将持续 30 个月至 2021 年 07 月，届时所有 V3.1.x 将停止更新维护。
+
+现有版本
+--------
+
+ESP8266 RTOS SDK V3.3 及所有后续更新版本都将遵守该《支持期限政策》。每一版本发布时将同时公布其支持期限。
+
+对于该政策公布之日前发布的其他版本，应适用下述支持期限：
+
+- ESP8266 RTOS SDK V3.3.x 将维护至 2021 年 12 月。
+- ESP8266 RTOS SDK V3.2.x 将维护至 2020 年 12 月。
+- ESP8266 RTOS SDK V3.1.x 作为长期维护版本，将维护至 2021 年 7 月。
+- ESP8266 RTOS SDK V3.0.x 将维护至 2020 年 10 月。
+- ESP8266 RTOS SDK V2.1.x 作为长期维护版本，将维护至 2021 年 4 月。
+- ESP8266 RTOS SDK V2.0.x 及之前的版本均已停止更新维护 (EOL)。
diff --git a/SUPPORT_POLICY_EN.md b/SUPPORT_POLICY_EN.md
@@ -0,0 +1,56 @@
+The latest support policy for ESP8266 RTOS SDK can be found at [Support Policy](./SUPPORT_POLICY_EN.md).
+
+Support Period Policy
+=================
+
+* [中文版](./SUPPORT_POLICY_CN.md)
+
+Each ESP8266 RTOS SDK major and minor release (V3.0, V3.1, etc) is supported for 18 months after the initial stable release date.
+
+Supported means that the ESP8266 RTOS SDK team will continue to apply bug fixes, security fixes, etc to the release branch on GitHub, and periodically make new bugfix releases as needed.
+
+Users are encouraged to upgrade to a newer ESP8266 RTOS SDK release before the support period finishes and the release becomes End of Life (EOL). It is our policy to not continue fixing bugs in End of Life releases.
+
+Pre-release versions (betas, previews, -rc and -dev versions, etc) are not covered by any support period. Sometimes a particular feature is marked as "Preview" in a release, which means it is also not covered by the support period.
+
+
+Long Term Support releases
+------------
+
+Some releases (for example, ESP8266 RTOS SDK V3.1) are designated Long Term Support (LTS). LTS releases are supported for 30 months (2.5 years) after the initial stable release date.
+
+We will add a `(LTS)` tag when we release a long term support version on GitHub at the first time. For example:
+
+```
+ESP8266 RTOS SDK Release v3.4 (LTS)
+```
+
+But we will not add `(LTS)` tag to the following bug fix versions. For example:
+
+```
+ESP8266 RTOS SDK Release v3.4.1
+```
+
+Example
+-----
+
+ESP8266 RTOS SDK V3.1 was released in January 2019 and is a Long Term Support (LTS) release, meaning it will be supported for 30 months until July 2021.
+
+- The first V3.1 release was `v3.1` in January 2019.
+- The ESP8266 RTOS SDK team continues to backport bug fixes, security fixes, etc to the release branch `release/v3.1`。
+- Periodically stable bugfix releases are created from the release branch. For example `v3.1.1`、`v3.1.2`, etc. Users are encouraged to always update to the latest bugfix release.
+- V3.1 bugfix releases continue until July 2021, when all V3.1.x releases become End of Life.
+
+Existing Releases
+--------
+
+ESP8266 RTOS SDK V3.3 and all newer releases will follow this support period policy. The support period for each release will be announced when the release is made.
+
+For releases made before the support period policy was announced, the following support periods apply:
+
+- ESP8266 RTOS SDK V3.2.x will be supported until December 2021.
+- ESP8266 RTOS SDK V3.2.x will be supported until December 2020.
+- ESP8266 RTOS SDK V3.1.x is Long Term Support (LTS) release, will be supported until July 2021.
+- ESP8266 RTOS SDK V3.0.x will be supported until October 2020.
+- ESP8266 RTOS SDK V2.1.x is Long Term Support (LTS) release, will be supported until April 2021.
+- ESP8266 RTOS SDK V2.0.x and earlier versions are already End of Life.
diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild
@@ -10,6 +10,15 @@ config BOOTLOADER_INIT_SPI_FLASH
         If your system bootloader is based on v3.0, the option must not be enable, because the v3.0 bootloader don't support
         this function.
 
+config BOOTLOADER_DISABLE_JTAG_IO
+    bool "Bootloader disable JTAG I/O"
+    default n 
+    help
+        Enable this option, when SoC brings up and bootloader initializes hardware, it will
+        disable JTAG's I/O and set these GPIOs to be normal I/O with inputting mode.
+
+        If users use JTAG to help develop, please disable this option.
+
 choice LOG_BOOTLOADER_LEVEL
    bool "Bootloader log verbosity"
    default LOG_BOOTLOADER_LEVEL_INFO
@@ -162,6 +171,14 @@ config BOOTLOADER_HOLD_TIME_GPIO
         The GPIO must be held low continuously for this period of time after reset 
         before a factory reset or test partition boot (as applicable) is performed.
 
+config BOOTLOADER_STORE_OFFSET
+    hex "Bootloader store offset in the flash"
+    default 0x0
+    help
+        Bootloader store offset in the flash, if you have extra private bootloader to boot the
+        bootloader of the SDK's bootloader, you can set the option to store SDK's bootloader
+        to other space in the flash instead of "0x0".
+
 endmenu  # Bootloader
 
 

diff --git a/components/bootloader/Makefile.projbuild b/components/bootloader/Makefile.projbuild
@@ -18,7 +18,7 @@ SECURE_BOOT_SIGNING_KEY=$(abspath $(call dequote,$(CONFIG_SECURE_BOOT_SIGNING_KE
 export SECURE_BOOT_SIGNING_KEY  # used by bootloader_support component
 
 # Has a matching value in bootloader_support esp_flash_partitions.h
-BOOTLOADER_OFFSET := 0x0000
+BOOTLOADER_OFFSET := $(CONFIG_BOOTLOADER_STORE_OFFSET)
 
 # Custom recursive make for bootloader sub-project
 #

diff --git a/components/bootloader_support/src/bootloader_flash.c b/components/bootloader_support/src/bootloader_flash.c
@@ -268,6 +268,12 @@ esp_err_t bootloader_flash_erase_sector(size_t sector)
 #include "esp_spi_flash.h"
 #endif
 
+#ifdef CONFIG_SOC_FULL_ICACHE
+#define SOC_CACHE_SIZE 1 // 32KB
+#else
+#define SOC_CACHE_SIZE 0 // 16KB
+#endif
+
 extern void Cache_Read_Disable();
 extern void Cache_Read_Enable(uint8_t map, uint8_t p, uint8_t v);
 
@@ -290,21 +296,48 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
         return NULL; /* can't map twice */
     }
 
-    /* ToDo: Improve the map policy! */
-
-    Cache_Read_Disable();
+    /* 0: 0x000000 - 0x1fffff */
+    /* 1: 0x200000 - 0x3fffff */
+    /* 2: 0x400000 - 0x5fffff */
+    /* 3: 0x600000 - 0x7fffff */
+
+    uint32_t region;
+    uint32_t sub_region;
+    uint32_t mapped_src;
+
+    if (src_addr < 0x200000) {
+        region = 0;
+    } else if (src_addr < 0x400000) {
+        region = 1;
+    } else if (src_addr < 0x600000) {
+        region = 2;
+    } else if (src_addr < 0x800000) {
+        region = 3;
+    } else {
+        ESP_LOGE(TAG, "flash mapped address %p is invalid", (void *)src_addr);
+        while (1);
+    }
 
-    /* 0 and 0x100000 address use same mmap addresss 0x40200000 */
-    if (src_addr < 0x100000) {
-        Cache_Read_Enable(0, 0, 0);
+    /* 0: 0x000000 - 0x0fffff \              */
+    /*                         \             */
+    /*                           0x40200000  */
+    /*                         /             */
+    /* 1: 0x100000 - 0x1fffff /              */
+    mapped_src =  src_addr & 0x1fffff;
+    if (mapped_src < 0x100000) {
+        sub_region = 0;
     } else {
-        Cache_Read_Enable(1, 0, 0);
-        src_addr -= 0x100000;
+        sub_region = 1;
+        mapped_src -= 0x100000;
     }
 
+    Cache_Read_Disable();
+
+    Cache_Read_Enable(sub_region, region, SOC_CACHE_SIZE);
+
     mapped = true;
 
-    return (void *)(0x40200000 + src_addr);
+    return (void *)(0x40200000 + mapped_src);
 }
 
 void bootloader_munmap(const void *mapping)

diff --git a/components/bootloader_support/src/bootloader_init.c b/components/bootloader_support/src/bootloader_init.c
@@ -613,6 +613,17 @@ esp_err_t bootloader_init()
 
 static esp_err_t bootloader_main()
 {
+#ifdef CONFIG_BOOTLOADER_DISABLE_JTAG_IO
+    /* Set GPIO 12-15 to be normal GPIO  */
+    PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, FUNC_GPIO12);
+    PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_GPIO13);
+    PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, FUNC_GPIO14);
+    PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_GPIO15);
+
+    /* Set GPIO 12-15 to be input mode  */
+    GPIO_REG_WRITE(GPIO_ENABLE_W1TC_ADDRESS, BIT12 | BIT13 | BIT14 | BIT15);
+#endif
+
     uart_console_configure();
 
     esp_image_header_t fhdr;

diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c
@@ -495,15 +495,6 @@ static void set_cache_and_start_app(
 #include "esp_flash_partitions.h"
 #include "internal/esp_system_internal.h"
 
-#ifdef CONFIG_SOC_FULL_ICACHE
-#define SOC_CACHE_SIZE 1 // 32KB
-#else
-#define SOC_CACHE_SIZE 0 // 16KB
-#endif
-
-#define ESP_CACHE1_ADDR_MAX 0x100000
-#define ESP_CACHE2_ADDR_MAX 0x200000
-
 static const char* TAG = "boot";
 
 bool bootloader_utility_load_partition_table(bootloader_state_t* bs)
@@ -803,7 +794,6 @@ bool bootloader_utility_load_boot_image(const bootloader_state_t *bs, int start_
 void bootloader_utility_load_image(const esp_image_metadata_t* image_data)
 {
     void (*user_start)(size_t start_addr);
-    extern void Cache_Read_Enable(uint8_t map, uint8_t p, uint8_t v);
 
 #if defined(CONFIG_SECURE_BOOT_ENABLED) || defined(CONFIG_FLASH_ENCRYPTION_ENABLED)
     esp_err_t err;
@@ -848,22 +838,7 @@ void bootloader_utility_load_image(const esp_image_metadata_t* image_data)
     copy loaded segments to RAM, set up caches for mapped segments, and start application
     unpack_load_app(image_data);
 #else
-    size_t map;
-
-    if (image_data->start_addr < ESP_CACHE1_ADDR_MAX
-        && image_data->start_addr + image_data->image_len < ESP_CACHE1_ADDR_MAX) { 
-        map = 0;
-    } else if (image_data->start_addr >= ESP_CACHE1_ADDR_MAX
-               && image_data->start_addr < ESP_CACHE2_ADDR_MAX
-               && image_data->start_addr + image_data->image_len < ESP_CACHE2_ADDR_MAX) {
-        map = 1;
-    } else {
-        ESP_LOGE(TAG, "ERROR: app bin error, start_addr %x image_len %d\n", image_data->start_addr, image_data->image_len);
-        /* Blocking here to let user judge. */
-        while (1);
-    }
-
-    Cache_Read_Enable(map, 0, SOC_CACHE_SIZE);
+    bootloader_mmap(image_data->start_addr, image_data->image_len);
 
     user_start = (void *)image_data->image.entry_addr;
     user_start(image_data->start_addr);

diff --git a/components/esp8266/Kconfig b/components/esp8266/Kconfig
@@ -472,9 +472,12 @@ config ESP_PHY_CALIBRATION_AND_DATA_STORAGE
     default y
     help
         If this option is enabled, NVS will be initialized and calibration data will be loaded from there.
-        PHY calibration will be skipped on deep sleep wakeup. If calibration data is not found, full calibration
-        will be performed and stored in NVS. Normally, only partial calibration will be performed. 
-        If this option is disabled, full calibration will be performed.
+        If calibration data is not found, full calibration will be performed and stored in NVS. Normally,
+        only partial calibration will be performed. If this option is disabled, full calibration will be performed.
+
+        Full calibration needs 170 - 180ms.
+        Partial calibration needs 35 - 40ms.
+        No calibration needs 3.260 - 3.264ms.
 
         If it's easy that your board calibrate bad data, choose 'n'.
         Two cases for example, you should choose 'n':

diff --git a/components/esp8266/driver/gpio.c b/components/esp8266/driver/gpio.c
@@ -86,7 +86,10 @@ static gpio_isr_func_t *gpio_isr_func = NULL;
 esp_err_t gpio_pullup_en(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
-    GPIO_CHECK(!RTC_GPIO_IS_VALID_GPIO(gpio_num), "The RTC GPIO of esp8266 can not be pulled up.", ESP_ERR_INVALID_ARG);
+
+    if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
+        return ESP_OK;
+    }
 
     gpio_pin_reg_t pin_reg;
     pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(gpio_num));
@@ -98,7 +101,10 @@ esp_err_t gpio_pullup_en(gpio_num_t gpio_num)
 esp_err_t gpio_pullup_dis(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
-    GPIO_CHECK(!RTC_GPIO_IS_VALID_GPIO(gpio_num), "The RTC GPIO of esp8266 can not be pulled up.", ESP_ERR_INVALID_ARG);
+
+    if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
+        return ESP_OK;
+    }
 
     gpio_pin_reg_t pin_reg;
     pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(gpio_num));
@@ -110,7 +116,10 @@ esp_err_t gpio_pullup_dis(gpio_num_t gpio_num)
 esp_err_t gpio_pulldown_en(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
-    GPIO_CHECK(RTC_GPIO_IS_VALID_GPIO(gpio_num), "The GPIO of esp8266 can not be pulled down except RTC GPIO.", ESP_ERR_INVALID_ARG);
+
+    if (!RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
+        return ESP_OK;
+    }
 
     gpio_pin_reg_t pin_reg;
     pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(gpio_num));
@@ -122,7 +131,10 @@ esp_err_t gpio_pulldown_en(gpio_num_t gpio_num)
 esp_err_t gpio_pulldown_dis(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
-    GPIO_CHECK(RTC_GPIO_IS_VALID_GPIO(gpio_num), "The GPIO of esp8266 can not be pulled down except RTC GPIO.", ESP_ERR_INVALID_ARG);
+
+    if (!RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
+        return ESP_OK;
+    }
 
     gpio_pin_reg_t pin_reg;
     pin_reg.val = READ_PERI_REG(GPIO_PIN_REG(gpio_num));

diff --git a/components/esp8266/driver/uart.c b/components/esp8266/driver/uart.c
@@ -419,6 +419,11 @@ esp_err_t uart_isr_register(uart_port_t uart_num, void (*fn)(void *), void *arg)
 {
     UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
 
+    for (int num = 0; num < UART_NUM_MAX; num++) {
+        if (p_uart_obj[num] == NULL) {
+            uart_disable_intr_mask(num, UART_INTR_MASK);
+        }
+    }
     UART_ENTER_CRITICAL();
     _xt_isr_mask(1 << ETS_UART_INUM);
     _xt_isr_attach(ETS_UART_INUM, uart_intr_service, NULL);
@@ -587,7 +592,12 @@ static void uart_rx_intr_handler_default(void *param)
                         }
 
                         if (p_uart->tx_len_tot == 0) {
-                            en_tx_flg = false;
+                            if (tx_fifo_rem == 0) {
+                                en_tx_flg = true;
+                            } else{
+                                en_tx_flg = false;
+                            }
+
                             xSemaphoreGiveFromISR(p_uart->tx_done_sem, &task_woken);
                             if (task_woken == pdTRUE) {
                                 portYIELD_FROM_ISR();

diff --git a/components/esp8266/include/esp8266/eagle_soc.h b/components/esp8266/include/esp8266/eagle_soc.h
@@ -117,6 +117,7 @@
 //}}
 
 //Interrupt remap control registers define{{
+#define NMI_INT_ENABLE_REG          (PERIPHS_DPORT_BASEADDR)
 #define EDGE_INT_ENABLE_REG         (PERIPHS_DPORT_BASEADDR + 0x04)
 #define WDT_EDGE_INT_ENABLE()       SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT0)
 #define TM1_EDGE_INT_ENABLE()       SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1)