feat(esp32c5): Add stub flasher support

espressif · Jul 10, 2024 · 3a8f92d · 3a8f92d
1 parent b8be327
commit 3a8f92d
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Showing 7 changed files with 553 additions and 15 deletions.
diff --git a/flasher_stub/Makefile b/flasher_stub/Makefile
@@ -68,6 +68,7 @@ STUB_ELF_32H2_BETA_1 = $(BUILD_DIR)/$(STUB)32h2beta1.elf
 STUB_ELF_32H2_BETA_2 = $(BUILD_DIR)/$(STUB)32h2beta2.elf
 STUB_ELF_32C2 = $(BUILD_DIR)/$(STUB)32c2.elf
 STUB_ELF_32C6 = $(BUILD_DIR)/$(STUB)32c6.elf
+STUB_ELF_32C5 = $(BUILD_DIR)/$(STUB)32c5.elf
 STUB_ELF_32C5_BETA_3 = $(BUILD_DIR)/$(STUB)32c5beta3.elf
 STUB_ELF_32H2 = $(BUILD_DIR)/$(STUB)32h2.elf
 STUB_ELF_32P4 = $(BUILD_DIR)/$(STUB)32p4.elf
@@ -94,6 +95,7 @@ STUBS_ELF += \
   $(STUB_ELF_32H2_BETA_2) \
   $(STUB_ELF_32C2) \
   $(STUB_ELF_32C6) \
+  $(STUB_ELF_32C5) \
   $(STUB_ELF_32C5_BETA_3) \
   $(STUB_ELF_32H2) \
   $(STUB_ELF_32P4)
@@ -171,6 +173,10 @@ $(STUB_ELF_32C6): $(SRCS) $(BUILD_DIR) ld/stub_32c6.ld
 	@echo "  CC(32C6)   $^ -> $@"
 	$(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32C6=1 -Tstub_32c6.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS)
 
+$(STUB_ELF_32C5): $(SRCS) $(BUILD_DIR) ld/stub_32c5.ld
+	@echo "  CC(32C5)   $^ -> $@"
+	$(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32C5=1 -Tstub_32c5.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS)
+
 $(STUB_ELF_32C5_BETA_3): $(SRCS) $(BUILD_DIR) ld/stub_32c5_beta_3.ld
 	@echo "  CC(32C5BETA3)   $^ -> $@"
 	$(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32C5BETA3=1 -Tstub_32c5_beta_3.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS)

diff --git a/flasher_stub/include/rom_functions.h b/flasher_stub/include/rom_functions.h
@@ -18,11 +18,11 @@ int uart_rx_one_char(uint8_t *ch);
 uint8_t uart_rx_one_char_block();
 int uart_tx_one_char(char ch);
 
-#if ESP32C6 || ESP32H2 || ESP32C5BETA3 || ESP32P4
+#if ESP32C6 || ESP32H2 || ESP32C5 || ESP32C5BETA3 || ESP32P4
 /* uart_tx_one_char doesn't send data to USB device serial, needs to be replaced */
 int uart_tx_one_char2(char ch);
 #define uart_tx_one_char(ch) uart_tx_one_char2(ch)
-#endif // ESP32C6 || ESP32H2 || ESP32C5BETA3 || ESP32P4
+#endif // ESP32C6 || ESP32H2 || ESP32C5 || ESP32C5BETA3 || ESP32P4
 
 void uart_div_modify(uint32_t uart_no, uint32_t baud_div);
 

diff --git a/flasher_stub/include/soc_support.h b/flasher_stub/include/soc_support.h
@@ -46,9 +46,14 @@
 #define WITH_USB_OTG 1
 #endif // ESP32S3
 
-#ifdef ESP32C5BETA3
+#ifdef ESP32C5
 #define WITH_USB_JTAG_SERIAL 1
 #define IS_RISCV 1
+#endif // ESP32C5
+
+#ifdef ESP32C5BETA3
+#define WITH_USB_JTAG_SERIAL 0
+#define IS_RISCV 1
 #endif // ESP32C5BETA3
 
 #ifdef ESP32C6
@@ -173,7 +178,7 @@
 #define DR_REG_IO_MUX_BASE  0x60009000
 #endif
 
-#if ESP32C6 || ESP32C5BETA3
+#if ESP32C6 || ESP32C5 || ESP32C5BETA3
 #define UART_BASE_REG       0x60000000 /* UART0 */
 #define SPI_BASE_REG        0x60003000 /* SPI peripheral 1, used for SPI flash */
 #define SPI0_BASE_REG       0x60002000 /* SPI peripheral 0, inner state machine */
@@ -333,14 +338,24 @@
 #define ETS_USB_INUM 17  /* arbitrary level 1 level interrupt */
 #endif // ESP32S3
 
-#if ESP32C6 || ESP32C5BETA3
+#if ESP32C6
 #define UART_USB_JTAG_SERIAL  3
 
 #define DR_REG_INTERRUPT_MATRIX_BASE            0x60010000
 #define INTERRUPT_CORE0_USB_INTR_MAP_REG        (DR_REG_INTERRUPT_MATRIX_BASE + 0xC0) /* USB-JTAG-Serial, INTMTX_CORE0_USB_INTR_MAP_REG */
 
 #define ETS_USB_INUM 17  /* arbitrary level 1 level interrupt */
-#endif // ESP32C6 || ESP32C5BETA3
+#endif // ESP32C6
+
+#if ESP32C5
+#define UART_USB_JTAG_SERIAL  3
+
+#define DR_REG_INTERRUPT_MATRIX_BASE            0x60010000
+#define INTERRUPT_CORE0_USB_INTR_MAP_REG        (DR_REG_INTERRUPT_MATRIX_BASE + 0xD0) /* USB-JTAG-Serial, INTMTX_CORE0_USB_INTR_MAP_REG */
+
+#define CLIC_EXT_INTR_NUM_OFFSET 16  /* For CLIC first 16 interrupts are reserved as internal */
+#define ETS_USB_INUM 17  /* arbitrary level 1 level interrupt */
+#endif // ESP32C5
 
 #ifdef ESP32H2
 #define UART_USB_JTAG_SERIAL  3
@@ -403,7 +418,7 @@
 #define RTC_CNTL_SWD_AUTO_FEED_EN     (1 << 31)
 #endif
 
-#if ESP32C6 || ESP32C5BETA3 || ESP32P4
+#if ESP32C6 || ESP32C5 || ESP32C5BETA3 || ESP32P4
 #define RTC_CNTL_WDTCONFIG0_REG       (DR_REG_LP_WDT_BASE + 0x0)   // LP_WDT_RWDT_CONFIG0_REG
 #define RTC_CNTL_WDTWPROTECT_REG      (DR_REG_LP_WDT_BASE + 0x0018)  // LP_WDT_RWDT_WPROTECT_REG
 #define RTC_CNTL_SWD_CONF_REG         (DR_REG_LP_WDT_BASE + 0x001C)  // LP_WDT_SWD_CONFIG_REG
@@ -456,6 +471,14 @@
 #define SYSTEM_SOC_CLK_MAX            1
 #endif // ESP32S2
 
+#ifdef ESP32C5
+#define PCR_SYSCLK_CONF_REG          (DR_REG_PCR_BASE + 0x10c)
+#define PCR_SOC_CLK_SEL_M            ((PCR_SOC_CLK_SEL_V)<<(PCR_SOC_CLK_SEL_S))
+#define PCR_SOC_CLK_SEL_V            0x3
+#define PCR_SOC_CLK_SEL_S            16
+#define PCR_SOC_CLK_MAX              3 // CPU_CLK frequency is 240 MHz (source is PLL_F240_CLK)
+#endif // ESP32C5
+
 #ifdef ESP32C5BETA3
 #define PCR_SYSCLK_CONF_REG          (DR_REG_PCR_BASE + 0x10c)
 #define PCR_SOC_CLK_SEL_M            ((PCR_SOC_CLK_SEL_V)<<(PCR_SOC_CLK_SEL_S))
@@ -501,9 +524,9 @@
 #define ROM_SPIFLASH_LEGACY         0x3ffae270
 #endif // ESP32 || ESP32S2 || ESP32S3 || ESP32S3BETA2
 
-#if ESP32C3 || ESP32C6BETA || ESP32C2 || ESP32C6 || ESP32C5BETA3
+#if ESP32C3 || ESP32C6BETA || ESP32C2 || ESP32C6 || ESP32C5 || ESP32C5BETA3
 #define ROM_SPIFLASH_LEGACY         0x3fcdfff4
-#endif // ESP32C3 || ESP32C6BETA || ESP32C2 || ESP32C6
+#endif // ESP32C3 || ESP32C6BETA || ESP32C2 || ESP32C6 || ESP32C5 || ESP32C5BETA3
 
 #if ESP32H2BETA1 || ESP32H2BETA2
 #define ROM_SPIFLASH_LEGACY         0x3fcdfff0
@@ -567,13 +590,13 @@
 #define FUNC_GPIO 1
 #endif // ESP32C2
 
-#if ESP32C6 || ESP32C6BETA || ESP32C5BETA3
+#if ESP32C6 || ESP32C6BETA || ESP32C5 || ESP32C5BETA3
 #define PERIPHS_IO_MUX_SPICLK_U           (DR_REG_IO_MUX_BASE + 0x78)
 #define PERIPHS_IO_MUX_SPIQ_U             (DR_REG_IO_MUX_BASE + 0x68)
 #define PERIPHS_IO_MUX_SPID_U             (DR_REG_IO_MUX_BASE + 0x7c)
 #define PERIPHS_IO_MUX_SPICS0_U           (DR_REG_IO_MUX_BASE + 0x64)
 #define FUNC_GPIO 1
-#endif // ESP32C6 || ESP32C6BETA
+#endif // ESP32C6 || ESP32C6BETA || ESP32C5 || ESP32C5BETA3
 
 #if ESP32H2 || ESP32H2BETA1 || ESP32H2BETA2
 #define PERIPHS_IO_MUX_SPICLK_U           (DR_REG_IO_MUX_BASE + 0x50)