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faramire / TT06-simple-stopwatch Public

generated from TinyTapeout/tt06-verilog-template

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gds

Added a clock divider and a 3 bit counter 0 -> 6 #2

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Added a clock divider and a 3 bit counter 0 -> 6

Added a clock divider and a 3 bit counter 0 -> 6 #2

Summary
Jobs
- gds
- precheck
- gl_test
- viewer
Run details
- Usage
- Workflow file

Usage Workflow file

Run time

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Job	Run time
gds	17s
viewer	0s
precheck	0s
gl_test	0s
	17s

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