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yosys -p "synth_ice40 -blif stopwatch.blif" tb_icestick.v | ||
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arachne-pnr -d 1k -p icestick.pcf stopwatch.blif -o stopwatch.txt | ||
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icepack stopwatch.txt stopwatch.bin | ||
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iceprog stopwatch.bin |
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module clockDividerIce ( | ||
input wire clk_in, // input clock 12 MHz | ||
input wire ena, | ||
input wire res, // reset, active low | ||
output reg clk_out // output clock 1 MHz | ||
); | ||
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reg[2:0] counter; | ||
parameter div = 6; // 12 MHz / 12 = 1 MHz, 50% duty cycle => 1/2 of that | ||
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always @(posedge clk_in) begin | ||
if (!res) begin // reset | ||
counter <= 3'b0; | ||
clk_out <= 1'b0; | ||
end else if (ena) begin | ||
if (counter < (div-1)) begin // count up | ||
counter <= counter + 1; | ||
end else begin // reset counter and invert output | ||
counter <= 3'b0; | ||
clk_out <= ~clk_out; | ||
end | ||
end | ||
end | ||
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endmodule //clockDividerIce |
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