Added a clock divider and a 3 bit counter 0 -> 6

info.yaml

@@ -5,7 +5,7 @@ project:
   discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  ""      # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
-  clock_hz:     50000000  # Clock frequency in Hz (or 0 if not applicable)
+  clock_hz:     1000000  # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2

src/clockdivider.v

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2024 Fabio Ramirez Stern
+ * SPDX-License-Identifier: Apache-2.0
+ ******************************************************
+ * Divides the 1 MHz clock to a 10 Hz clock
+ */
+
+`define default_netname none
+
+ module clockDivider (
+    input  wire clk_in,
+    input  wire res,
+    input  wire ena,
+    output wire clk_out
+ );
+    reg[16:0] counter =      0;
+    parameter div     = 100000; // 1 MHz / 100'000 = 10 Hz
+
+    always @(posedge clk_in or res) begin
+        if (!res) begin     // async reset
+            counter <= 0;
+            clk_out <= 0;
+        end else begin
+            if (counter < (div-1)) begin    // count up
+                counter <= counter + 1;
+            end else begin                  // reset counter and invert output
+                counter <= 0;
+                clk_out <= ~clk_out;
+            end 
+        end
+    end
+ endmodule

src/counter6.v

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2024 Fabio Ramirez Stern
+ * SPDX-License-Identifier: Apache-2.0
+ ******************************************************
+ * Counts up to 6
+ */
+
+`define default_netname none
+
+ module counter6 (
+    input  wire       clk, // clock
+    input  wire       ena, // enable
+    input  wire       res, // reset
+    output wire       max, // high when max value (6) reached
+    output wire [2:0] cnt  // 3 bit counter output
+ )
+
+    reg[2:0] counter    = 0;
+    parameter max_count = 6;
+
+    always @(posedge clk_in or res) begin
+        if (!res) begin     // async reset
+            cnt <= 0;
+            max <= 0;
+        end else if (ena) begin
+            if (cnt < max_count - 1) begin
+                cnt <= cnt + 1;
+            end else begin
+                cnt <= 0;
+            end
+        end
+    end
+
+    always @(cnt) begin
+        if (cnt == max_count) begin
+            max <= 1;
+        end else begin
+            max <= 0;
+        end
+    end
+
+ endmodule

src/draft.v

@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2024 Fabio Ramirez Stern
+ * Copyright (c) 2024 Fabio Ramirez Stern
  * SPDX-License-Identifier: Apache-2.0
  */