made all resets synchronous

src/SPI_wrapper.v

@@ -31,12 +31,11 @@ module SPI_wrapper (
 
   reg [15:0] word_out;
   reg [2:0] digit_count;
-  reg [1:0] setup_count;
   wire send_reported;
   wire ready_reported;
   reg reset_master;
 
-  always @(posedge clk or negedge res) begin  // controlling FSM
+  always @(posedge clk) begin  // controlling FSM
     if (!res) begin // active low reset
       Cs <= 1;
       reset_master <= 0;
@@ -149,7 +148,7 @@ module SPI_wrapper (
     .report_send(send_reported),
     .report_ready(ready_reported),
 
-    .sck(clk_SPI),
+    .sck(Clk_SPI),
     .mosi(Mosi)
   );
 

src/stopwatch_top.v

@@ -97,7 +97,7 @@ module clockDivider (
   parameter div     = 5000; // 1 MHz / 10'000 = 100 Hz, 50% duty cycle => 1/2 of that
 
 
-  always @(posedge clk_in or negedge res) begin
+  always @(posedge clk_in) begin
     if (!res) begin     // async reset
       counter <= 14'b0;
       clk_out <= 1'b0;
@@ -119,14 +119,14 @@ module controller (
   output reg  display_enable  //
 );
 
-  always @(posedge start_stop or negedge res) begin
+  always @(posedge start_stop) begin
     if (!res)
       counter_enable <= 1'b0;
     else
       counter_enable <= ~counter_enable;
   end
 
-  always @(posedge lap_time or negedge res) begin
+  always @(posedge lap_time) begin
     if (!res)
       display_enable <= 1'b1;
     else
@@ -145,7 +145,7 @@ module counter6 (
 
 parameter max_count = 6;
 
-  always @(posedge clk or negedge res) begin
+  always @(posedge clk) begin
     if (!res) begin
       cnt <= 3'b0;
       max <= 1'b0;
@@ -176,7 +176,7 @@ module counter10 (
 
   parameter max_count = 10;
 
-  always @(posedge clk or negedge res) begin
+  always @(posedge clk) begin
     if (!res) begin
       cnt <= 4'b0;
       max <= 1'b0;