added external testbench

src/stopwatch_top.v

@@ -213,6 +213,8 @@ module counter_chain (
   wire min_0X_ena;
   wire min_X0_ena;
 
+  wire max; // just something to connect the unused max pin of the last counter to something
+
   counter10 inst_ces_0X ( // counts first digit centiseconds
     .clk (clk), // clock in
     .ena (ena), // enable
@@ -257,7 +259,7 @@ module counter_chain (
     .clk (clk),
     .ena (ena & ces_X0_ena & sec_0X_ena & sec_X0_ena & min_0X_ena & min_X0_ena),
     .res (res),
-    .max (),
+    .max (max),
     .cnt (min_X0)
   );
 

test/tb_8bitworkshop.v

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2024 Fabio Ramirez Stern
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`define default_netname none
+`include "tt_um_faramire_stopwatch.v"
+module stopwatch (
+  input wire clk,
+  input wire reset_board,
+  input wire button_start_stop,
+  input wire button_lap_time,
+  input wire button_reset,
+
+  output wire mosi,
+  output wire cs,
+  output wire sck,
+  output wire stopwatch_enabled,
+  output wire display_enabled
+);
+
+  reg [7:0] sink1;
+
+  tt_um_faramire_stopwatch stopwatch1 (
+    .ui_in({5'b0, button_reset, button_lap_time, button_start_stop}),
+    .uo_out({3'b0, display_enabled, stopwatch_enabled, sck, cs, mosi}),
+    .uio_in(8'b0),
+    .uio_out(sink1),
+    .uio_oe(sink1),
+    .ena(1),
+    .clk(clk),
+    .rst_n(reset_board)
+  );
+endmodule