major rewrites of nearly all modules

src/SPI_driver.v

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2024 Fabio Ramirez Stern
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`define default_netname none
+
+module SPI_driver (
+    input wire clk,
+    input wire [2:0] min_X0, // minutes
+    input wire [3:0] min_0X,
+    input wire [2:0] sec_X0, // seconds
+    input wire [3:0] sec_0X,
+    input wire [3:0] ces_X0, // centiseconds (100th)
+    input wire [3:0] ces_0X,
+    output wire clk_SPI,
+    output wire MOSI
+ );
+
+endmodule

src/clockdivider.v

@@ -7,26 +7,26 @@
 
 `define default_netname none
 
- module clockDivider (
-    input  wire clk_in,
-    input  wire res,
-    input  wire ena,
-    output wire clk_out
+module clockDivider (
+    input wire clk_in, // input clock 1 MHz
+    input wire res,    // async reset, active low
+    output reg clk_out // output clock 100 Hz
  );
+
     reg[13:0] counter =    0;
     parameter div     = 5000; // 1 MHz / 10'000 = 100 Hz, 50% duty cycle => 1/2 of that
 
-    always @(posedge clk_in or res) begin
+
+    always @(posedge clk_in or negedge res) begin
         if (!res) begin     // async reset
             counter <= 0;
             clk_out <= 0;
-        end else begin
-            if (counter < (div-1)) begin    // count up
-                counter <= counter + 1;
-            end else begin                  // reset counter and invert output
-                counter <= 0;
-                clk_out <= ~clk_out;
-            end 
+        end else if (counter < (div-1)) begin    // count up
+            counter <= counter + 1;
+        end else begin                  // reset counter and invert output
+            counter <= 0;
+            clk_out <= ~clk_out; 
         end
     end
- endmodule
+
+endmodule

src/controller.v

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2024 Fabio Ramirez Stern
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`define default_netname none
+
+module controller (
+    input  wire res,            // reset, active low
+    input  wire start_stop,     // impulse toggles counter_enable
+    input  wire lap_time,       // impulse toggles display_enable
+    output reg  counter_enable, // 
+    output reg  display_enable  //
+ );
+
+    always @(posedge start_stop or negedge res) begin
+        if (!res)
+            counter_enable <= 0;
+        else
+            counter_enable <= ~counter_enable;
+    end
+
+    always @(posedge lap_time or negedge res) begin
+        if (!res)
+            display_enable <= 1;
+        else
+            display_enable <= ~display_enable;
+    end
+
+endmodule

src/counter10.v

@@ -7,36 +7,34 @@
 
 `define default_netname none
 
- module counter6 (
-    input  wire       clk, // clock
-    input  wire       ena, // enable
-    input  wire       res, // reset
-    output wire       max, // high when max value (10) reached
-    output wire [3:0] cnt  // 4 bit counter output
- )
+module counter10 (
+    input  wire      clk, // clock
+    input  wire      ena, // enable
+    input  wire      res, // reset, active low
+    output reg       max, // high when max value (10) reached
+    output reg [3:0] cnt  // 3 bit counter output
+ );
 
     reg[3:0] counter    = 0;
     parameter max_count = 10;
 
-    always @(posedge clk_in or res) begin
-        if (!res) begin     // async reset
+    always @(posedge clk or negedge res) begin
+        if (!res) begin
             cnt <= 0;
             max <= 0;
         end else if (ena) begin
-            if (cnt < max_count - 1) begin
+            if (cnt < (max_count-1)) begin
                 cnt <= cnt + 1;
             end else begin
                 cnt <= 0;
             end
-        end
-    end
 
-    always @(cnt) begin
-        if (cnt == max_count) begin
-            max <= 1;
-        end else begin
-            max <= 0;
+          if (cnt == max_count-2) begin
+            	max <= 1;
+            end else begin
+                max <= 0;
+            end
         end
     end
 
- endmodule
+endmodule

src/counter6.v

@@ -7,36 +7,34 @@
 
 `define default_netname none
 
- module counter6 (
-    input  wire       clk, // clock
-    input  wire       ena, // enable
-    input  wire       res, // reset
-    output wire       max, // high when max value (6) reached
-    output wire [2:0] cnt  // 3 bit counter output
- )
+module counter6 (
+    input  wire      clk, // clock
+    input  wire      ena, // enable
+    input  wire      res, // reset, active low
+    output reg       max, // high when max value (6) reached
+    output reg [2:0] cnt  // 3 bit counter output
+ );
 
     reg[2:0]  counter   = 0;
     parameter max_count = 6;
 
-    always @(posedge clk_in or res) begin
-        if (!res) begin     // async reset
+    always @(posedge clk or negedge res) begin
+        if (!res) begin
             cnt <= 0;
             max <= 0;
         end else if (ena) begin
-            if (cnt < max_count - 1) begin
+            if (cnt < (max_count-1)) begin
                 cnt <= cnt + 1;
             end else begin
                 cnt <= 0;
             end
-        end
-    end
 
-    always @(cnt) begin
-        if (cnt == max_count) begin
-            max <= 1;
-        end else begin
-            max <= 0;
+          if (cnt == max_count-2) begin
+            	max <= 1;
+            end else begin
+                max <= 0;
+            end
         end
     end
 
- endmodule
+endmodule

src/counter_chain.v

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2024 Fabio Ramirez Stern
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`define default_netname none
+
+module counter_chain (
+    input wire clk,
+    output wire [2:0] min_X0, // minutes
+    output wire [3:0] min_0X,
+    output wire [2:0] sec_X0, // seconds
+    output wire [3:0] sec_0X,
+    output wire [3:0] ces_X0, // centiseconds (100th)
+    output wire [3:0] ces_0X
+ );
+
+
+endmodule

src/draft.v → src/top_draft.v

@@ -17,11 +17,28 @@ module tt_um_faramire_lcd_stopwatch_draft (
     input  wire       ena,      // will go high when the design is enabled
     input  wire       clk,      // clock
     input  wire       rst_n     // reset_n - low to reset
-);
-
+ );
   // All output pins must be assigned. If not used, assign to 0.
-  assign uo_out  = ui_in + uio_in;  // Example: ou_out is the sum of ui_in and uio_in
   assign uio_out = 0;
   assign uio_oe  = 0;
 
+  wire dividedClock; // 100 Hz clock
+  wire counter_enable;
+  wire display_enable;
+
+  wire [2:0] min_X0; // all the results of the counter chain
+  wire [3:0] min_0X;
+  wire [2:0] sec_X0;
+  wire [3:0] sec_0X;
+  wire [3:0] ces_X0;
+  wire [3:0] ces_0X;
+
+  clockDivider inst1 (
+    .clk_in  (clk),
+    .res     (rst_n),
+    .clk_out (dividedClock)
+  );
+
+
+
 endmodule