added rotary decoder and did some setup config

.gitignore

@@ -10,3 +10,4 @@ test/sim_build
 test/__pycache__/
 test/results.xml
 test/gate_level_netlist.v
+*.v.out

info.yaml

@@ -5,17 +5,17 @@ project:
   discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  "A rotary encoder controls 12 WS2812B LEDs on a ring PCB."      # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
-  clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
+  clock_hz:     40000000  # 40MHz Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
-  top_module:  "tt_um_faramire_ws2812b_wrapper"
+  top_module:  "tt_um_faramire_rotary_ring_wrapper"
 
   # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
   source_files:        
-    - "project.v"
+    - "rotary_ring_wrapper.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:

src/debounce.v

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024 Fabio Ramirez Stern
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`default_nettype none
+
+module debounce (
+  input wire clock, // clock
+  input wire res_n, // active low reset
+  input wire in,    // the input to be debounced
+  output reg out    // debounced output
+);
+
+
+  always @(posedge clock) begin
+
+    if (!res_n) begin
+      //
+    end
+
+  end
+endmodule

src/rotary_decoder.v

@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2024 Fabio Ramirez Stern
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`default_nettype none
+
+module rotary_decoder (
+
+  /*
+  * Rotary Encoder Decoder
+  * Takes the two outputs of a rotary coder and determines in which direction it was turned. Output as one hod encoding.
+  * rotary_clk and rotary_dt can be swapped to change direction, their connection should be arbitrary.
+  */
+
+  input wire clk, // 40MHz clock
+  input wire res_n, // active low reset
+  input wire rotary_clk, // output labeled clk of the rotary encoder (active low)
+  input wire rotary_dt,  // output labeled dt  of the rotary encoder (active low)
+  output reg rotation_up,  // goes high for one clock cycle if rotated upwards (clockwise)
+  output reg rotation_dn   // goes high for one clock cycle if rotated downwards (counter clockwise)
+);
+
+  reg up_detected;
+  reg dn_detected;
+  reg [1:0] state;
+
+  // FSM states
+  localparam DETECTING = 2'b00;
+  localparam OUTPUT    = 2'b01;
+  localparam PAUSE     = 2'b10;
+  localparam WAIT      = 2'b11;
+
+  // Pause counter
+  reg [15:0] pause_counter;
+
+  always @(posedge clk) begin // process to monitor encoder
+
+    if (!res_n) begin // reset
+      rotation_up <= 0;
+      rotation_dn <= 0;
+      state <= DETECTING;
+    end else begin
+
+      case(state) // FSM
+
+        DETECTING: begin
+          if (!rotary_clk) begin // movement detected
+            if (!rotary_dt) begin // rotary_dt already high => up movement
+              up_detected <= 1;
+              dn_detected <= 0;
+              state <= OUTPUT;
+            end else begin       // rotary_dt still low => down movement
+              up_detected <= 0;
+              dn_detected <= 1;
+              state <= OUTPUT;
+            end
+          end
+        end // DETECTING
+
+        OUTPUT: begin // copy the detected state to the outputs and go to next state where they will be set to 0 again => on for one clock
+          rotation_up <= up_detected;
+          rotation_dn <= dn_detected;
+          pause_counter = 16'b0;
+          state <= PAUSE;
+        end //OUTPUT
+
+        PAUSE: begin // pause for 1 ms to debounce (40k clock cycles)
+          rotation_up <= 0;
+          rotation_dn <= 0;
+          if (pause_counter == 16'b1001_1100_0011_1111) begin
+            state <= WAIT;
+          end else begin
+            pause_counter = pause_counter + 16'b1;
+          end
+        end // PAUSE
+
+        WAIT: begin // wait until both inputs are high again, then transition to detecting again
+          if (rotary_clk && rotary_dt) begin
+            state <= DETECTING;
+          end          
+        end // WAIT
+
+        default:;
+      endcase
+
+    end
+
+  end
+endmodule

src/project.v → src/rotary_ring_wrapper.v

@@ -1,11 +1,14 @@
 /*
- * Copyright (c) 2024 Your Name
+ * Copyright (c) 2024 Fabio Ramirez Stern
  * SPDX-License-Identifier: Apache-2.0
  */
 
 `default_nettype none
+`include "rotary_decoder.v"
+`include "position_counter.v"
+`include ""
 
-module tt_um_faramire_ws2812b_wrapper (
+module tt_um_faramire_rotary_ring_wrapper (
     input  wire [7:0] ui_in,    // Dedicated inputs
     output wire [7:0] uo_out,   // Dedicated outputs
     input  wire [7:0] uio_in,   // IOs: Input path

test/Makefile

@@ -5,7 +5,8 @@
 SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 SRC_DIR = $(PWD)/../src
-PROJECT_SOURCES = project.v
+PROJECT_SOURCES = rotary_ring_wrapper.v
+
 
 ifneq ($(GATES),yes)
 

test/tb.v

@@ -24,7 +24,7 @@ module tb ();
   wire [7:0] uio_oe;
 
   // Replace tt_um_example with your module name:
-  tt_um_faramire_ws2812b_wrapper user_project (
+  tt_um_faramire_rotary_ring_wrapper user_project (
 
       // Include power ports for the Gate Level test:
 `ifdef GL_TEST