RVSV is a SystemVerilog implementation of a 5-stage pipelined RISC-V CPU.
- systemverilog/rv32i_seq.sv (sequential implementation)
- systemverilog/rv32i_pipe.sv (5-stage pipelined implementation)
- Rust
- Verilator
- CMake (version 3.14 or higher)
For simulation and testing, we use verilator to create verilated models that are then connected to our C++ testsuits (inside testsuits folder). Within the testsuis, we use rubbler to generate test instructions from assembly lines. Execute the following commands to run all test.
git clone https://github.com/fuad1502/rvsv.git
cd rvsv
cmake -Bbuild -S.
cmake --build build
cd build
ctest