clk2fflogic: run peepopt -formalclk before processing design

* this attempts to rewrite clock gating patterns into a form that is less likely to introduce combinational loops with clk2fflogic
georgerennie · Aug 7, 2024 · a4f60de · a4f60de
1 parent 52ee9c5
commit a4f60de
Showing 1 changed file with 4 additions and 0 deletions.
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
@@ -135,6 +135,10 @@ struct Clk2fflogicPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
+		log_push();
+		Pass::call(design, "peepopt -formalclk");
+		log_pop();
+
 		bool have_check_cells = false;
 
 		for (auto module : design->selected_modules())