vhdl writeline messages not printed

[laurentiuduca]

hello, i have also noticed that debug messages (for example writeline) from vhdl sources
are not printed to the console during simulation with cxxrtl

is there any way to see the vhdl messages printed
considering verilog-vhdl mixed simulation?

[tgingold]

I don't think that is possible.

cxxrtl works by first synthesizing your design and then simulating the netlist. Debug messages are lost during this process.

[laurentiuduca]

hi, the $display and $write from verilog are printed in the console in cxxrtl

…

On Wed, Nov 27, 2024 at 8:24 AM tgingold ***@***.***> wrote: I don't think that is possible. cxxrtl works by first synthesizing your design and then simulating the netlist. Debug messages are lost during this process. — Reply to this email directly, view it on GitHub <#202 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AKBRLNYUT3E24XSNQGVKGOT2CVQTBAVCNFSM6AAAAABSQLC73OVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDKMBTGAYDONZYGQ> . You are receiving this because you authored the thread.Message ID: ***@***.***>

[tgingold]

Ok, I will have a second look. But I fear handling writeline is much more difficult than $display, as it deals with access variables. But if cxxrtl is handling $display, at least report and assert support could be improved.