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various optis, maybe unsafe
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GliGli authored and tuxuser committed Feb 29, 2012
1 parent bbd7343 commit 4799962
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Showing 7 changed files with 57 additions and 37 deletions.
2 changes: 2 additions & 0 deletions nullDC/dc/sh4/rec_v1/basicblock.h
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Expand Up @@ -81,6 +81,8 @@ class BasicBlock: public CodeRegion

u32 IsDelaySlot:1;
u32 SaveTInDelaySlot:1;
u32 CouldNeedPCtmp:1;
u32 NeedPCtmp:1;
};
}flags; //compiled block flags :)

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1 change: 1 addition & 0 deletions nullDC/dc/sh4/rec_v1/driver.cpp
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Expand Up @@ -193,6 +193,7 @@ void naked DynaMainLoop()

//
"lis " xstr(RSH4R) ",sh4r@ha \n"
"lis " xstr(RROML) ",0xe000 \n"
"lwz " xstr(RPC) ",0(" xstr(RSH4R) ") \n"//sh4r+0 is pc

//Max cycle count :)
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2 changes: 1 addition & 1 deletion nullDC/dc/sh4/rec_v1/driver.h
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Expand Up @@ -7,7 +7,7 @@
#define FRONE 15
#define FRHALF 14
#define RCYCLES 13
#define RPCTMPVAL 14
#define RROML 14
#define RPC 15
#define CPU_TIMESLICE (BLOCKLIST_MAX_CYCLES)

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67 changes: 44 additions & 23 deletions nullDC/dc/sh4/rec_v1/sh4_cpu_shil.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -20,11 +20,14 @@ shil_stream* ilst;

#define handle_stids {if (bb->flags.IsDelaySlot) { bb->flags.SaveTInDelaySlot=true; ilst->LoadT(jcond_flag); } }

#define need_rpctmp {if (bb->flags.IsDelaySlot && bb->flags.CouldNeedPCtmp) { printf("need_rpctmp\n"); bb->flags.NeedPCtmp=true; ilst->mov(reg_pc_temp, reg_pc); } }
#define handle_rpctmp {if (bb->flags.NeedPCtmp) { printf("handle_rpctmp\n"); ilst->mov(reg_pc, reg_pc_temp); } }


//#define tmu_underflow 0x0100
#define iNimp(info) rec_shil_iNimp(pc,op,info)

#define shil_interpret(str) ilst->shil_ifb(str,pc);
#define shil_interpret(str) { need_rpctmp; ilst->shil_ifb(str,pc); }

Sh4RegType dyna_reg_id_r[16];
Sh4RegType dyna_reg_id_r_bank[8];
Expand Down Expand Up @@ -1420,14 +1423,16 @@ rsh4op(icpu_nimp)

//Branches

void DoDslot(u32 pc,BasicBlock* bb)
void DoDslot(u32 pc,BasicBlock* bb, bool CouldNeedPCtmp)
{
u16 opcode=ReadMem16(pc+2);

if (opcode==0 || opcode==0)
log("0 on delayslot , ingoring it ..\n");
else{
bb->flags.IsDelaySlot=true;
bb->flags.CouldNeedPCtmp=CouldNeedPCtmp;
bb->flags.NeedPCtmp=false;
RecOpPtr[opcode](opcode,pc+2,bb);
bb->flags.IsDelaySlot=false;
}
Expand All @@ -1436,6 +1441,8 @@ void DoDslot(u32 pc,BasicBlock* bb)
//braf <REG_N>
rsh4op(i0000_nnnn_0010_0011)
{
need_rpctmp;

u32 n = GetN(op);
/*
u32 newpc = r[n] + pc + 2;//pc +2 is done after
Expand All @@ -1448,14 +1455,16 @@ rsh4op(i0000_nnnn_0010_0011)
//return;
bb->flags.ExitType = BLOCK_EXITTYPE_DYNAMIC;
bb->flags.EndAnalyse=true;
ilst->mov(reg_pc_temp,r[n]);
ilst->add(reg_pc_temp,pc+4);
DoDslot(pc,bb);
ilst->mov(reg_pc,reg_pc_temp);
ilst->mov(reg_pc,r[n]);
ilst->add(reg_pc,pc+4);
DoDslot(pc,bb,true);
handle_rpctmp;
}
//bsrf <REG_N>
rsh4op(i0000_nnnn_0000_0011)
{
need_rpctmp;

u32 n = GetN(op);
/*
u32 newpc = r[n] + pc +2;//pc +2 is done after
Expand All @@ -1473,17 +1482,19 @@ rsh4op(i0000_nnnn_0010_0011)
bb->flags.EndAnalyse=true;
bb->flags.ExitType=BLOCK_EXITTYPE_DYNAMIC_CALL;
ilst->mov(reg_pr,pc+4);
ilst->mov(reg_pc_temp,r[n]);
ilst->add(reg_pc_temp,pc+4);
DoDslot(pc,bb);
ilst->mov(reg_pc,reg_pc_temp);
ilst->mov(reg_pc,r[n]);
ilst->add(reg_pc,pc+4);
DoDslot(pc,bb,true);
handle_rpctmp;
bb->TT_next_addr=pc+4;
}


//rte
rsh4op(i0000_0000_0010_1011)
{
need_rpctmp;

/*
//iNimp("rte");
sr.SetFull(ssr);
Expand All @@ -1505,6 +1516,8 @@ rsh4op(i0000_nnnn_0010_0011)
//rts
rsh4op(i0000_0000_0000_1011)
{
need_rpctmp;

/*
//TODO Check new delay slot code [28/1/06]
u32 newpc=pr;//+2 is added after instruction
Expand All @@ -1517,9 +1530,9 @@ rsh4op(i0000_nnnn_0010_0011)
//return;
bb->flags.EndAnalyse = true;
bb->flags.ExitType= BLOCK_EXITTYPE_RET;
ilst->mov(reg_pc_temp,reg_pr);
DoDslot(pc,bb);
ilst->mov(reg_pc,reg_pc_temp);
ilst->mov(reg_pc,reg_pr);
DoDslot(pc,bb,true);
handle_rpctmp;
}


Expand Down Expand Up @@ -1564,7 +1577,7 @@ rsh4op(i0000_nnnn_0010_0011)
bb->TF_next_addr=pc+4;
bb->TT_next_addr=(u32)((GetSImm8(op))*2 + 4 + pc );

DoDslot(pc,bb);
DoDslot(pc,bb,false);
bb->flags.EndAnalyse = true;
bb->flags.ExitType = BLOCK_EXITTYPE_COND;
}
Expand Down Expand Up @@ -1609,7 +1622,7 @@ rsh4op(i0000_nnnn_0010_0011)
bb->TF_next_addr=(u32)((GetSImm8(op))*2 + 4 + pc );
bb->TT_next_addr=pc+4;

DoDslot(pc,bb);
DoDslot(pc,bb,false);

bb->flags.EndAnalyse=true;
bb->flags.ExitType=BLOCK_EXITTYPE_COND;
Expand All @@ -1630,7 +1643,7 @@ rsh4op(i1010_iiii_iiii_iiii)
bb->TF_next_addr=(u32) (( ((s16)((GetImm12(op))<<4)) >>3) + pc + 4);
bb->flags.EndAnalyse=true;
bb->flags.ExitType=BLOCK_EXITTYPE_FIXED;
DoDslot(pc,bb);
DoDslot(pc,bb,false);
}
// bsr <bdisp12>
rsh4op(i1011_iiii_iiii_iiii)
Expand All @@ -1650,13 +1663,15 @@ rsh4op(i1011_iiii_iiii_iiii)
bb->flags.ExitType=BLOCK_EXITTYPE_FIXED_CALL;

ilst->mov(reg_pr,pc+4);
DoDslot(pc,bb);
DoDslot(pc,bb,false);
bb->TT_next_addr=pc+4;
}

// trapa #<imm>
rsh4op(i1100_0011_iiii_iiii)
{
need_rpctmp;

/*
CCN_TRA = (GetImm8(op) << 2);
Do_Exeption(0,0x160,0x100);
Expand All @@ -1670,6 +1685,8 @@ rsh4op(i1100_0011_iiii_iiii)
//jmp @<REG_N>
rsh4op(i0100_nnnn_0010_1011)
{ //ToDo : Check Me [26/4/05] | Check new delay slot code [28/1/06]
need_rpctmp;

u32 n = GetN(op);
/*
//delay 1 instruction
Expand All @@ -1683,24 +1700,26 @@ rsh4op(i1100_0011_iiii_iiii)
//return;
bb->flags.EndAnalyse=true;
bb->flags.ExitType=BLOCK_EXITTYPE_DYNAMIC;
ilst->mov(reg_pc_temp,r[n]);
DoDslot(pc,bb);
ilst->mov(reg_pc,reg_pc_temp);
ilst->mov(reg_pc,r[n]);
DoDslot(pc,bb,true);
handle_rpctmp;
}


//jsr @<REG_N>
rsh4op(i0100_nnnn_0000_1011)
{//ToDo : Check This [26/4/05] | Check new delay slot code [28/1/06]
need_rpctmp;

u32 n = GetN(op);


bb->flags.EndAnalyse=true;
bb->flags.ExitType=BLOCK_EXITTYPE_DYNAMIC_CALL;
ilst->mov(reg_pr,pc+4);
ilst->mov(reg_pc_temp,r[n]);
DoDslot(pc,bb);
ilst->mov(reg_pc,reg_pc_temp);
ilst->mov(reg_pc,r[n]);
DoDslot(pc,bb,true);
handle_rpctmp;
bb->TT_next_addr=pc+4;
}

Expand All @@ -1714,6 +1733,8 @@ rsh4op(sh4_bpt_op)
//sleep
rsh4op(i0000_0000_0001_1011)
{
need_rpctmp;

shil_interpret(op);
ilst->add(reg_pc,2);
bb->flags.EndAnalyse=true;
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16 changes: 7 additions & 9 deletions nullDC/dc/sh4/shil/compiler/shil_compiler_base.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1365,22 +1365,21 @@ void roml(ppc_reg reg,ppc_Label* lbl,u32* offset_Edit,int size,int rw)
case FLAG_16: EMIT_XORI(ppce,R6,reg,2); reg=R6; break;
}

#if 1

#if 0
ppce->emitLoadImmediate32(R5,0xE0000000);
EMIT_CMPL(ppce,reg,R5,0);
ppce->emitBranchConditionalToLabel(lbl,0,PPC_CC_F,PPC_CC_NEG);
EMIT_RLWINM(ppce,R5,reg,0,3,31);
EMIT_ORIS(ppce,R5,R5,(u32)sh4_reserved_mem>>16);
#else
ppce->emitLoadImmediate32(R7,0x20000000);
#else
PowerPC_instr ppc;
GEN_ADD(ppc,R5,R7,reg);
GEN_SUBF(ppc,R5,RROML,reg);
ppc|=1;
ppce->write32(ppc);

ppce->emitBranchConditionalToLabel(lbl,0,PPC_CC_F,PPC_CC_NEG);
EMIT_RLWIMI(ppce,R5,R7,1,0,2);
EMIT_RLWIMI(ppce,R5,RSH4R,31,0,2); // RSH4R is 0x8xxxxxxx, it's the only reason it's used here
#endif
}
//const ppc_opcode_class rm_table[4]={op_movsx8to32,op_movsx16to32,op_mov32,op_movlps};
Expand Down Expand Up @@ -1667,7 +1666,6 @@ void apply_roml_patches()
{
if (roml_patch_list[i].is_float)
{
//meh ?
if (roml_patch_list[i].type==1)
{
static u32 tmp;
Expand Down Expand Up @@ -2875,7 +2873,7 @@ void __fastcall shil_compile_shil_ifb(shil_opcode* op)
ira->FlushRegCache();
#endif

fra->FlushRegCache();
if (op->imm1>=0xf000) fra->FlushRegCache();

#ifdef PROF_IFB
ppce->emitLoad32(R3,&op_usage[op->imm1]);
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2 changes: 0 additions & 2 deletions nullDC/emitter/regalloc/ppc_intregalloc.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -101,8 +101,6 @@ class SimpleGPRAlloc : public IntegerRegAllocator

if (i<REG_ALLOC_COUNT)
r_alloced[i].ppcreg=reg_to_alloc[i];
else if (i==reg_pc_temp)
r_alloced[i].ppcreg=(ppc_reg)RPCTMPVAL;
else if (i==reg_pc)
r_alloced[i].ppcreg=(ppc_reg)RPC;

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4 changes: 2 additions & 2 deletions nullDC/nullDC.cpp
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Expand Up @@ -232,13 +232,13 @@ void LoadSettings()
settings.dynarec.Enable=1; //gli cfgLoadInt(_T"nullDC",_T"Dynarec.Enabled",1)!=0;
settings.dynarec.CPpass=1; //gli cfgLoadInt(_T"nullDC",_T"Dynarec.DoConstantPropagation",1)!=0;
settings.dynarec.Safe=1; //gli cfgLoadInt(_T"nullDC",_T"Dynarec.SafeMode",1)!=0;
settings.dynarec.UnderclockFpu=cfgLoadInt(_T"nullDC",_T"Dynarec.UnderclockFpu",0)!=0;
settings.dynarec.UnderclockFpu=1; //gli cfgLoadInt(_T"nullDC",_T"Dynarec.UnderclockFpu",0)!=0;

settings.dreamcast.cable=0; //gli cfgLoadInt(_T"nullDC",_T"Dreamcast.Cable",3);
settings.dreamcast.RTC=cfgLoadInt(_T"nullDC",_T"Dreamcast.RTC",GetRTC_now());

settings.dreamcast.region=1; //gli USA cfgLoadInt(_T"nullDC",_T"Dreamcast.Region",3);
settings.dreamcast.broadcast=4; //hli cfgLoadInt(_T"nullDC",_T"Dreamcast.Broadcast",4);
settings.dreamcast.broadcast=4; //gli cfgLoadInt(_T"nullDC",_T"Dreamcast.Broadcast",4);

settings.emulator.AutoStart=1; //gli cfgLoadInt(_T"nullDC",_T"Emulator.AutoStart",0)!=0;
settings.emulator.NoConsole=cfgLoadInt(_T"nullDC",_T"Emulator.NoConsole",0)!=0;
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