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No need to specify translation regime anymore.
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It is implied by the Attributes type.
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@qwandor
qwandor committed Sep 24, 2024
1 parent 22d19e0 commit 62d439c
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Showing 5 changed files with 53 additions and 149 deletions.
38 changes: 16 additions & 22 deletions src/idmap.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@
use crate::{
paging::{
attributes::Attributes, deallocate, Constraints, Descriptor, MemoryRegion, PageTable,
PhysicalAddress, Translation, TranslationRegime, VaRange, VirtualAddress,
PhysicalAddress, Translation, VaRange, VirtualAddress,
},
MapError, Mapping,
};
Expand Down Expand Up @@ -65,7 +65,7 @@ impl<A: Attributes> Translation<A> for IdTranslation {
/// ```no_run
/// use aarch64_paging::{
/// idmap::IdMap,
/// paging::{attributes::AttributesEl1, MemoryRegion, TranslationRegime},
/// paging::{attributes::AttributesEl1, MemoryRegion},
/// };
///
/// const ASID: usize = 1;
Expand All @@ -74,7 +74,7 @@ impl<A: Attributes> Translation<A> for IdTranslation {
/// AttributesEl1::ATTRIBUTE_INDEX_1.union(AttributesEl1::INNER_SHAREABLE);
///
/// // Create a new EL1 page table with identity mapping.
/// let mut idmap = IdMap::new(ASID, ROOT_LEVEL, TranslationRegime::El1And0);
/// let mut idmap = IdMap::new(ASID, ROOT_LEVEL);
/// // Map a 2 MiB region of memory as read-write.
/// idmap
/// .map_range(
Expand Down Expand Up @@ -122,15 +122,9 @@ pub struct IdMap<A: Attributes> {

impl<A: Attributes> IdMap<A> {
/// Creates a new identity-mapping page table with the given ASID and root level.
pub fn new(asid: usize, rootlevel: usize, translation_regime: TranslationRegime) -> Self {
pub fn new(asid: usize, rootlevel: usize) -> Self {
Self {
mapping: Mapping::new(
IdTranslation,
asid,
rootlevel,
translation_regime,
VaRange::Lower,
),
mapping: Mapping::new(IdTranslation, asid, rootlevel, VaRange::Lower),
}
}

Expand Down Expand Up @@ -356,7 +350,7 @@ mod tests {
#[test]
fn map_valid() {
// A single byte at the start of the address space.
let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0);
let mut idmap = IdMap::new(1, 1);
// SAFETY: This doesn't actually activate the page table in tests, it just treats it as
// active for the sake of BBM rules.
unsafe {
Expand All @@ -371,7 +365,7 @@ mod tests {
);

// Two pages at the start of the address space.
let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0);
let mut idmap = IdMap::new(1, 1);
// SAFETY: This doesn't actually activate the page table in tests, it just treats it as
// active for the sake of BBM rules.
unsafe {
Expand All @@ -386,7 +380,7 @@ mod tests {
);

// A single byte at the end of the address space.
let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0);
let mut idmap = IdMap::new(1, 1);
// SAFETY: This doesn't actually activate the page table in tests, it just treats it as
// active for the sake of BBM rules.
unsafe {
Expand All @@ -404,7 +398,7 @@ mod tests {
);

// Two pages, on the boundary between two subtables.
let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0);
let mut idmap = IdMap::new(1, 1);
// SAFETY: This doesn't actually activate the page table in tests, it just treats it as
// active for the sake of BBM rules.
unsafe {
Expand All @@ -419,7 +413,7 @@ mod tests {
);

// The entire valid address space.
let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0);
let mut idmap = IdMap::new(1, 1);
// SAFETY: This doesn't actually activate the page table in tests, it just treats it as
// active for the sake of BBM rules.
unsafe {
Expand All @@ -437,7 +431,7 @@ mod tests {
#[test]
fn map_break_before_make() {
const BLOCK_SIZE: usize = PAGE_SIZE << BITS_PER_LEVEL;
let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0);
let mut idmap = IdMap::new(1, 1);
idmap
.map_range_with_constraints(
&MemoryRegion::new(BLOCK_SIZE, 2 * BLOCK_SIZE),
Expand All @@ -460,7 +454,7 @@ mod tests {
Ok(())
);

let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0);
let mut idmap = IdMap::new(1, 1);
idmap
.map_range(
&MemoryRegion::new(BLOCK_SIZE, 2 * BLOCK_SIZE),
Expand Down Expand Up @@ -600,7 +594,7 @@ mod tests {

#[test]
fn map_out_of_range() {
let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0);
let mut idmap = IdMap::new(1, 1);

// One byte, just past the edge of the valid range.
assert_eq!(
Expand Down Expand Up @@ -629,7 +623,7 @@ mod tests {
}

fn make_map() -> IdMap<AttributesEl1> {
let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0);
let mut idmap = IdMap::new(1, 1);
idmap
.map_range(
&MemoryRegion::new(0, PAGE_SIZE * 2),
Expand Down Expand Up @@ -701,7 +695,7 @@ mod tests {
#[test]
fn breakup_invalid_block() {
const BLOCK_RANGE: usize = 0x200000;
let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0);
let mut idmap = IdMap::new(1, 1);
// SAFETY: This doesn't actually activate the page table in tests, it just treats it as
// active for the sake of BBM rules.
unsafe {
Expand Down Expand Up @@ -740,7 +734,7 @@ mod tests {
/// When an unmapped entry is split into a table, all entries should be zero.
#[test]
fn split_table_zero() {
let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0);
let mut idmap = IdMap::new(1, 1);

idmap
.map_range(
Expand Down
41 changes: 13 additions & 28 deletions src/lib.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@
//! # #[cfg(feature = "alloc")] {
//! use aarch64_paging::{
//! idmap::IdMap,
//! paging::{attributes::AttributesEl1, MemoryRegion, TranslationRegime},
//! paging::{attributes::AttributesEl1, MemoryRegion},
//! };
//!
//! const ASID: usize = 1;
Expand All @@ -28,7 +28,7 @@
//! AttributesEl1::ATTRIBUTE_INDEX_1.union(AttributesEl1::INNER_SHAREABLE);
//!
//! // Create a new EL1 page table with identity mapping.
//! let mut idmap = IdMap::new(ASID, ROOT_LEVEL, TranslationRegime::El1And0);
//! let mut idmap = IdMap::new(ASID, ROOT_LEVEL);
//! // Map a 2 MiB region of memory as read-write.
//! idmap
//! .map_range(
Expand Down Expand Up @@ -68,8 +68,8 @@ use core::arch::asm;
use core::fmt::{self, Display, Formatter};
use paging::{
attributes::{Attributes, CommonAttributes},
Constraints, Descriptor, MemoryRegion, PhysicalAddress, RootTable, Translation,
TranslationRegime, VaRange, VirtualAddress,
Constraints, Descriptor, MemoryRegion, PhysicalAddress, RootTable, Translation, VaRange,
VirtualAddress,
};

/// An error attempting to map some range in the page table.
Expand Down Expand Up @@ -131,18 +131,15 @@ pub struct Mapping<T: Translation<A>, A: Attributes> {

impl<T: Translation<A>, A: Attributes> Mapping<T, A> {
/// Creates a new page table with the given ASID, root level and translation mapping.
pub fn new(
translation: T,
asid: usize,
rootlevel: usize,
translation_regime: TranslationRegime,
va_range: VaRange,
) -> Self {
if !translation_regime.supports_asid() && asid != 0 {
panic!("{:?} doesn't support ASID, must be 0.", translation_regime);
pub fn new(translation: T, asid: usize, rootlevel: usize, va_range: VaRange) -> Self {
if !A::TRANSLATION_REGIME.supports_asid() && asid != 0 {
panic!(
"{:?} doesn't support ASID, must be 0.",
A::TRANSLATION_REGIME
);
}
Self {
root: RootTable::new(translation, rootlevel, translation_regime, va_range),
root: RootTable::new(translation, rootlevel, va_range),
asid,
previous_ttbr: None,
}
Expand Down Expand Up @@ -539,25 +536,13 @@ mod tests {
#[test]
#[should_panic]
fn no_el2_asid() {
Mapping::<IdTranslation, AttributesEl2>::new(
IdTranslation,
1,
1,
TranslationRegime::El2,
VaRange::Lower,
);
Mapping::<IdTranslation, AttributesEl2>::new(IdTranslation, 1, 1, VaRange::Lower);
}

#[cfg(feature = "alloc")]
#[test]
#[should_panic]
fn no_el3_asid() {
Mapping::<IdTranslation, AttributesEl3>::new(
IdTranslation,
1,
1,
TranslationRegime::El3,
VaRange::Lower,
);
Mapping::<IdTranslation, AttributesEl3>::new(IdTranslation, 1, 1, VaRange::Lower);
}
}
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