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Update zerocopy requirement from 0.7.35 to 0.8.2 #60

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Oct 7, 2024
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4 changes: 4 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,10 @@

## Unreleased

### Breaking changes

- Updated to `zerocopy` 0.8.2.

### New features

- Added `mair` module with types to build MAIR values.
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2 changes: 1 addition & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ categories = ["embedded", "no-std", "hardware-support"]

[dependencies]
bitflags = "2.6.0"
zerocopy = { version = "0.7.35", features = ["derive"], optional = true }
zerocopy = { version = "0.8.2", features = ["derive"], optional = true }

[features]
default = ["alloc", "zerocopy"]
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22 changes: 17 additions & 5 deletions src/paging.rs
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ use core::marker::PhantomData;
use core::ops::{Add, Range, Sub};
use core::ptr::NonNull;
#[cfg(feature = "zerocopy")]
use zerocopy::{AsBytes, FromBytes, FromZeroes};
use zerocopy::{FromBytes, FromZeros, Immutable, IntoBytes, KnownLayout};

const PAGE_SHIFT: usize = 12;

Expand Down Expand Up @@ -64,7 +64,10 @@ impl TranslationRegime {
}

/// An aarch64 virtual address, the input type of a stage 1 page table.
#[cfg_attr(feature = "zerocopy", derive(AsBytes, FromBytes, FromZeroes))]
#[cfg_attr(
feature = "zerocopy",
derive(FromBytes, Immutable, IntoBytes, KnownLayout)
)]
#[derive(Copy, Clone, Eq, Ord, PartialEq, PartialOrd)]
#[repr(transparent)]
pub struct VirtualAddress(pub usize);
Expand Down Expand Up @@ -111,7 +114,10 @@ pub struct MemoryRegion(Range<VirtualAddress>);

/// An aarch64 physical address or intermediate physical address, the output type of a stage 1 page
/// table.
#[cfg_attr(feature = "zerocopy", derive(AsBytes, FromBytes, FromZeroes))]
#[cfg_attr(
feature = "zerocopy",
derive(FromBytes, Immutable, IntoBytes, KnownLayout)
)]
#[derive(Copy, Clone, Eq, Ord, PartialEq, PartialOrd)]
#[repr(transparent)]
pub struct PhysicalAddress(pub usize);
Expand Down Expand Up @@ -834,7 +840,10 @@ impl<T: Translation> PageTableWithLevel<T> {

/// A single level of a page table.
#[repr(C, align(4096))]
#[cfg_attr(feature = "zerocopy", derive(AsBytes, FromZeroes))]
#[cfg_attr(
feature = "zerocopy",
derive(FromZeros, Immutable, IntoBytes, KnownLayout)
)]
pub struct PageTable {
entries: [Descriptor; 1 << BITS_PER_LEVEL],
}
Expand All @@ -856,7 +865,10 @@ impl PageTable {
/// - A page mapping, if it is in the lowest level page table.
/// - A block mapping, if it is not in the lowest level page table.
/// - A pointer to a lower level pagetable, if it is not in the lowest level page table.
#[cfg_attr(feature = "zerocopy", derive(AsBytes, FromZeroes))]
#[cfg_attr(
feature = "zerocopy",
derive(FromZeros, Immutable, IntoBytes, KnownLayout)
)]
#[derive(Clone, Copy, PartialEq, Eq)]
#[repr(C)]
pub struct Descriptor(usize);
Expand Down
2 changes: 1 addition & 1 deletion src/target.rs
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ use crate::paging::{deallocate, PageTable, PhysicalAddress, Translation};
use alloc::{vec, vec::Vec};
use core::{mem::size_of, ptr::NonNull};
#[cfg(feature = "zerocopy")]
use zerocopy::AsBytes;
use zerocopy::IntoBytes;

/// An implementation of `Translation` which builds a static pagetable to be built into a binary for
/// some target device.
Expand Down
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