Linting ruby code into one commit

google · Feb 8, 2023 · b2293b2 · b2293b2
1 parent 85a7664
commit b2293b2
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diff --git a/.github/workflows/linting.yml b/.github/workflows/linting.yml
@@ -21,12 +21,20 @@ on:
 jobs:
   lint_python:
     runs-on: ubuntu-latest
-    strategy:
-      max-parallel: 12
     steps:
       - uses: actions/checkout@v3
         with:
           submodules: 'recursive'
       - name: Lint with flake8
         run: |
-          make lint
+          make lint_python
+
+  lint_ruby:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v3
+        with:
+          submodules: 'recursive'
+      - name: Lint with rubocop
+        run: |
+          make lint_ruby
diff --git a/.github/workflows/regression.yml b/.github/workflows/regression.yml
@@ -45,7 +45,6 @@ jobs:
     needs: build_drc-matrix
     runs-on: ubuntu-latest
     strategy:
-      max-parallel: 4
       fail-fast: false
       matrix:
         part: [drc]
@@ -64,7 +63,6 @@ jobs:
   drc_switch:
     runs-on: ubuntu-latest
     strategy:
-      max-parallel: 4
       fail-fast: false
       matrix:
         include:
@@ -83,7 +81,6 @@ jobs:
   lvs_regression:
     runs-on: ubuntu-latest
     strategy:
-      max-parallel: 4
       fail-fast: false
       matrix:
         include:

diff --git a/.rubocop.yml b/.rubocop.yml
@@ -0,0 +1,45 @@
+# The behavior of RuboCop can be controlled via the .rubocop.yml
+# configuration file. It makes it possible to enable/disable
+# certain cops (checks) and to alter their behavior if they accept
+# any parameters. The file can be placed either in your home
+# directory or in some project directory.
+#
+# RuboCop will start looking for the configuration file in the directory
+# where the inspected file is and continue its way up to the root directory.
+#
+# See https://docs.rubocop.org/rubocop/configuration
+
+Style/FrozenStringLiteralComment:
+  Enabled: false
+
+GlobalVars:
+  Description: Do not introduce global variables.
+  Enabled: false
+
+UselessAssignment:
+  Description: Useless assignment to variable.
+  Enabled: false
+
+Metrics/AbcSize:
+  Description: Assignment Branch Condition size for conn_space is too high.
+  Enabled: false
+
+Metrics/MethodLength:
+  Description: Method has too many lines.
+  Enabled: false
+
+RSpec/VariableName:
+  Description: Use snake_case for variable names.
+  EnforcedStyle: "snake_case"
+  Enabled: false
+
+Metrics/BlockNesting:
+  Description:  Avoid more than 3 levels of block nesting.
+  Enabled: false
+
+AllCops:
+  Exclude:
+    - 'env/**/*'
+  Include:
+    - '**/*.rb'
+    - '**/*.drc'
diff --git a/Makefile b/Makefile
@@ -25,12 +25,19 @@ ENVIRONMENT_FILE := pdk_regression.yml
 # Path to regression
 KLAYOUT_TESTS := klayout/drc/testing/
 
+
 include third_party/make-env/conda.mk
 
 # Lint python code
-lint: | $(CONDA_ENV_PYTHON)
+lint_python: | $(CONDA_ENV_PYTHON)
 	@$(IN_CONDA_ENV) flake8 .
 
+# Lint ruby code
+lint_ruby:| $(CONDA_ENV_PYTHON)
+	@$(IN_CONDA_ENV) gem install rubocop
+	@ln -s $$CONDA_PREFIX/bin/ruby $$CONDA_PREFIX/share/rubygems/bin/ruby
+	@$(IN_CONDA_ENV) rubocop .
+
 ################################################################################
 ## DRC Regression section
 ################################################################################

diff --git a/klayout/drc/rule_decks/dualgate.drc b/klayout/drc/rule_decks/dualgate.drc
@@ -15,74 +15,73 @@
 ################################################################################################
 
 if FEOL
-    #================================================
-    #--------------------DUALGATE--------------------
-    #================================================
+  #================================================
+  #--------------------DUALGATE--------------------
+  #================================================
 
-    # Rule DV.1: Min. Dualgate enclose DNWELL. is 0.5µm
-    logger.info("Executing rule DV.1")
-    dv1_l1 = dualgate.enclosing(dnwell, 0.5.um, euclidian).polygons(0.001)
-    dv1_l2 = dnwell.not_outside(dualgate).not(dualgate)
-    dv1_l  = dv1_l1.or(dv1_l2)
-    dv1_l.output("DV.1", "DV.1 : Min. Dualgate enclose DNWELL. : 0.5µm")
-    dv1_l1.forget
-    dv1_l2.forget
-    dv1_l.forget
+  # Rule DV.1: Min. Dualgate enclose DNWELL. is 0.5µm
+  logger.info('Executing rule DV.1')
+  dv1_l1 = dualgate.enclosing(dnwell, 0.5.um, euclidian).polygons(0.001)
+  dv1_l2 = dnwell.not_outside(dualgate).not(dualgate)
+  dv1_l  = dv1_l1.or(dv1_l2)
+  dv1_l.output('DV.1', 'DV.1 : Min. Dualgate enclose DNWELL. : 0.5µm')
+  dv1_l1.forget
+  dv1_l2.forget
+  dv1_l.forget
 
-    # Rule DV.2: Min. Dualgate Space. Merge if Space is less than this design rule. is 0.44µm
-    logger.info("Executing rule DV.2")
-    dv2_l1  = dualgate.space(0.44.um, euclidian).polygons(0.001)
-    dv2_l1.output("DV.2", "DV.2 : Min. Dualgate Space. Merge if Space is less than this design rule. : 0.44µm")
-    dv2_l1.forget
+  # Rule DV.2: Min. Dualgate Space. Merge if Space is less than this design rule. is 0.44µm
+  logger.info('Executing rule DV.2')
+  dv2_l1 = dualgate.space(0.44.um, euclidian).polygons(0.001)
+  dv2_l1.output('DV.2', 'DV.2 : Min. Dualgate Space. Merge if Space is less than this design rule. : 0.44µm')
+  dv2_l1.forget
 
-    # Rule DV.3: Min. Dualgate to COMP space [unrelated]. is 0.24µm
-    logger.info("Executing rule DV.3")
-    dv3_l1  = dualgate.separation(comp.outside(dualgate), 0.24.um, euclidian).polygons(0.001)
-    dv3_l1.output("DV.3", "DV.3 : Min. Dualgate to COMP space [unrelated]. : 0.24µm")
-    dv3_l1.forget
+  # Rule DV.3: Min. Dualgate to COMP space [unrelated]. is 0.24µm
+  logger.info('Executing rule DV.3')
+  dv3_l1 = dualgate.separation(comp.outside(dualgate), 0.24.um, euclidian).polygons(0.001)
+  dv3_l1.output('DV.3', 'DV.3 : Min. Dualgate to COMP space [unrelated]. : 0.24µm')
+  dv3_l1.forget
 
-    # rule DV.4 is not a DRC check
-    # Refer to: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_07.html
+  # rule DV.4 is not a DRC check
+  # Refer to: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_07.html
 
-    # Rule DV.5: Min. Dualgate width. is 0.7µm
-    logger.info("Executing rule DV.5")
-    dv5_l1  = dualgate.width(0.7.um, euclidian).polygons(0.001)
-    dv5_l1.output("DV.5", "DV.5 : Min. Dualgate width. : 0.7µm")
-    dv5_l1.forget
+  # Rule DV.5: Min. Dualgate width. is 0.7µm
+  logger.info('Executing rule DV.5')
+  dv5_l1 = dualgate.width(0.7.um, euclidian).polygons(0.001)
+  dv5_l1.output('DV.5', 'DV.5 : Min. Dualgate width. : 0.7µm')
+  dv5_l1.forget
 
-    comp_dv = comp.not(pcomp.outside(nwell))
-    # Rule DV.6: Min. Dualgate enclose COMP (except substrate tap). is 0.24µm
-    logger.info("Executing rule DV.6")
-    dv6_l1 = dualgate.enclosing(comp_dv, 0.24.um, euclidian).polygons(0.001)
-    dv6_l2 = comp_dv.not_outside(dualgate).not(dualgate)
-    dv6_l  = dv6_l1.or(dv6_l2)
-    dv6_l.output("DV.6", "DV.6 : Min. Dualgate enclose COMP (except substrate tap). : 0.24µm")
-    dv6_l1.forget
-    dv6_l2.forget
-    dv6_l.forget
+  comp_dv = comp.not(pcomp.outside(nwell))
+  # Rule DV.6: Min. Dualgate enclose COMP (except substrate tap). is 0.24µm
+  logger.info('Executing rule DV.6')
+  dv6_l1 = dualgate.enclosing(comp_dv, 0.24.um, euclidian).polygons(0.001)
+  dv6_l2 = comp_dv.not_outside(dualgate).not(dualgate)
+  dv6_l  = dv6_l1.or(dv6_l2)
+  dv6_l.output('DV.6', 'DV.6 : Min. Dualgate enclose COMP (except substrate tap). : 0.24µm')
+  dv6_l1.forget
+  dv6_l2.forget
+  dv6_l.forget
 
-    # Rule DV.7: COMP (except substrate tap) can not be partially overlapped by Dualgate.
-    logger.info("Executing rule DV.7")
-    dv7_l1 = dualgate.not_outside(comp_dv).not(dualgate.covering(comp_dv))
-    dv7_l1.output("DV.7", "DV.7 : COMP (except substrate tap) can not be partially overlapped by Dualgate.")
-    dv7_l1.forget
+  # Rule DV.7: COMP (except substrate tap) can not be partially overlapped by Dualgate.
+  logger.info('Executing rule DV.7')
+  dv7_l1 = dualgate.not_outside(comp_dv).not(dualgate.covering(comp_dv))
+  dv7_l1.output('DV.7', 'DV.7 : COMP (except substrate tap) can not be partially overlapped by Dualgate.')
+  dv7_l1.forget
 
-    comp_dv.forget
+  comp_dv.forget
 
-    # Rule DV.8: Min Dualgate enclose Poly2. is 0.4µm
-    logger.info("Executing rule DV.8")
-    dv8_l1 = dualgate.enclosing(poly2, 0.4.um, euclidian).polygons(0.001)
-    dv8_l2 = poly2.not_outside(dualgate).not(dualgate)
-    dv8_l  = dv8_l1.or(dv8_l2)
-    dv8_l.output("DV.8", "DV.8 : Min Dualgate enclose Poly2. : 0.4µm")
-    dv8_l1.forget
-    dv8_l2.forget
-    dv8_l.forget
-
-    # Rule DV.9: 3.3V and 5V/6V PMOS cannot be sitting inside same NWELL.
-    logger.info("Executing rule DV.9")
-    dv9_l1 = nwell.covering(pgate.and(dualgate)).covering(pgate.not_inside(v5_xtor).not_inside(dualgate))
-    dv9_l1.output("DV.9", "DV.9 : 3.3V and 5V/6V PMOS cannot be sitting inside same NWELL.")
-    dv9_l1.forget
-end #FEOL
+  # Rule DV.8: Min Dualgate enclose Poly2. is 0.4µm
+  logger.info('Executing rule DV.8')
+  dv8_l1 = dualgate.enclosing(poly2, 0.4.um, euclidian).polygons(0.001)
+  dv8_l2 = poly2.not_outside(dualgate).not(dualgate)
+  dv8_l  = dv8_l1.or(dv8_l2)
+  dv8_l.output('DV.8', 'DV.8 : Min Dualgate enclose Poly2. : 0.4µm')
+  dv8_l1.forget
+  dv8_l2.forget
+  dv8_l.forget
 
+  # Rule DV.9: 3.3V and 5V/6V PMOS cannot be sitting inside same NWELL.
+  logger.info('Executing rule DV.9')
+  dv9_l1 = nwell.covering(pgate.and(dualgate)).covering(pgate.not_inside(v5_xtor).not_inside(dualgate))
+  dv9_l1.output('DV.9', 'DV.9 : 3.3V and 5V/6V PMOS cannot be sitting inside same NWELL.')
+  dv9_l1.forget
+end