Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Adding SRAM5p0 table for GF180MCU DRC #62

Merged
merged 2 commits into from
Apr 6, 2023
Merged

Conversation

FaragElsayed2
Copy link
Collaborator

Adding SRAM5p0 table for GF180MCU DRC

Fixes #43

@mithro mithro assigned proppy and unassigned proppy Apr 3, 2023
@mithro mithro requested a review from proppy April 3, 2023 17:32
@proppy
Copy link
Member

proppy commented Apr 4, 2023

@atorkmabrains can you review it first?

@atorkmabrains
Copy link
Collaborator

@proppy responded #65

Copy link
Collaborator

@atorkmabrains atorkmabrains left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@FaragElsayed2 Thanks for the update.

# limitations under the License.
################################################################################################

if FEOL
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

#58 but not blocking


if FEOL
#================================================
#--------------------5V SRAM---------------------
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

#57 but not blocking

sdf4c_l1.forget
sdf4c_l2.forget
sdf4c_l.forget
pcomp_out_dn_sram.forget
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

#53 but not blocking

# Rule S.DF.4c_MV: Min. (Nwell overlap of PCOMP) outside DNWELL. is 0.45µm
logger.info('Executing rule S.DF.4c_MV')
pcomp_out_dn_sram = pcomp.outside(dnwell).and(sram_mv)
sdf4c_l1 = pcomp_out_dn_sram.enclosed(nw_n_dn_sram, 0.45.um, euclidian).polygons(0.001.um)
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

why do we have .001 here?

Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

filed #66 to discuss this further


# Rule S.DF.8_MV: Min. (LVPWELL overlap of NCOMP) Inside DNWELL. is 0.45µm
logger.info('Executing rule S.DF.8_MV')
sdf8_l1 = ncomp_dn_sram.enclosed(lvpwell_dn_sram, 0.45.um, euclidian).polygons(0.001.um)
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

why do we have .001 here?

Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

filed #66 to discuss this further


# Rule S.CO.4_MV: COMP overlap of contact. is 0.04µm
logger.info('Executing rule S.CO.4_MV')
sco4_l1 = contact_sram.enclosed(comp_sram, 0.04.um, euclidian).polygons(0.001.um)
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

why do we have .001 here?

Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

filed #66 to discuss this further

Copy link
Member

@proppy proppy left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

just some nits and questions but nothing blocking per se, I'll leave it up to you if you want to address those in this PR or file separate issues to track them.

@atorkmabrains
Copy link
Collaborator

@proppy I have answered all the questions you have mentioned above in another PR.

@proppy proppy merged commit 2699532 into google:main Apr 6, 2023
@atorkmabrains atorkmabrains deleted the sram5p0_google branch April 6, 2023 10:55
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

Creating PRs for each DRC table separately
3 participants