Merge pull request #65 from mndza/fix-selftest-hyperram

selftest.gateware: Fix HyperRAM reads in comb domain
greatscottgadgets · Mar 8, 2024 · f39fe0d · f39fe0d
2 parents 9521094 + d0c7b70
commit f39fe0d
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Showing 2 changed files with 5 additions and 2 deletions.
diff --git a/cynthion/python/src/selftest/gateware.py b/cynthion/python/src/selftest/gateware.py
@@ -72,7 +72,11 @@ def elaborate(self, platform):
         psram_address_changed = Signal()
         psram_address = registers.add_register(REGISTER_RAM_REG_ADDR, write_strobe=psram_address_changed)
 
-        registers.add_sfr(REGISTER_RAM_VALUE, read=psram.read_data)
+        # Store last read word from HyperRAM.
+        psram_read_data = Signal.like(psram.read_data)
+        with m.If(psram.read_ready):
+            m.d.sync += psram_read_data.eq(psram.read_data)
+        registers.add_sfr(REGISTER_RAM_VALUE, read=psram_read_data)
 
         # Hook up our PSRAM.
         m.d.comb += [

diff --git a/cynthion/python/src/selftest/host.py b/cynthion/python/src/selftest/host.py
@@ -87,7 +87,6 @@ def assertPhyPresence(self, register_base: int):
     def assertHyperRAMRegister(self, address: int, expected_values: int):
         """ Assertion that fails iff a RAM register doesn't hold the expected value. """
 
-        self.dut.registers.register_write(REGISTER_RAM_REG_ADDR, address)
         self.dut.registers.register_write(REGISTER_RAM_REG_ADDR, address)
         actual_value =  self.dut.registers.register_read(REGISTER_RAM_VALUE)