Merge pull request #278 from miek/amaranth-0.5

Update to Amaranth 0.5
greatscottgadgets · Jan 30, 2025 · 3ad4155 · 3ad4155
2 parents ccc9cac + ca97c7e
commit 3ad4155
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Showing 50 changed files with 130 additions and 861 deletions.
diff --git a/applets/clear_endpoint_halt_test.py b/applets/clear_endpoint_halt_test.py
@@ -31,7 +31,7 @@
 COUNTER_MAX = 251
 GET_OUT_COUNTER_VALID = 0
 
-out_counter_valid = Signal(reset=1)
+out_counter_valid = Signal(init=1)
 
 class VendorRequestHandler(ControlRequestHandler):
 
@@ -137,7 +137,7 @@ def elaborate(self, platform):
                 m.d.usb += in_counter.eq(0)
 
         # Expect a counter on the OUT endpoint, and verify that it is contiguous.
-        prev_out_counter = Signal(8, reset=COUNTER_MAX)
+        prev_out_counter = Signal(8, init=COUNTER_MAX)
         with m.If(stream_out_ep.stream.valid):
             out_counter = stream_out_ep.stream.payload
             counter_increase = out_counter == (prev_out_counter + 1)

diff --git a/applets/hyperram_diagnostic.py b/applets/hyperram_diagnostic.py
@@ -69,7 +69,7 @@ def elaborate(self, platform):
         m.submodules.registers = registers
 
         psram_address = registers.add_register(REGISTER_RAM_ADDR)
-        read_length   = registers.add_register(REGISTER_RAM_READ_LENGTH, reset=1)
+        read_length   = registers.add_register(REGISTER_RAM_READ_LENGTH, init=1)
 
         m.submodules.read_fifo  = read_fifo  = SyncFIFO(width=REG_WIDTH, depth=32)
         m.submodules.write_fifo = write_fifo = SyncFIFO(width=REG_WIDTH, depth=32)

diff --git a/applets/ulpi-test.py b/applets/ulpi-test.py
diff --git a/examples/debugging/basic_ila.py b/examples/debugging/basic_ila.py
diff --git a/examples/debugging/basic_ila_fast_domain.py b/examples/debugging/basic_ila_fast_domain.py