replace window interface by registers

* Replace the IFFIFO window interface by plain status/control registers
* Add acceleration feature in IFFIFO
* Adapt software example
* Rename exported DMA slots

hw/core-v-mini-mcu/ao_peripheral_subsystem.sv

@@ -120,8 +120,8 @@ module ao_peripheral_subsystem
     output reg_req_t ext_peripheral_slave_req_o,
     input  reg_rsp_t ext_peripheral_slave_resp_i,
 
-    input logic ext_dma_slot_0_i,
-    input logic ext_dma_slot_1_i
+    input logic ext_dma_slot_tx_i,
+    input logic ext_dma_slot_rx_i
 );
 
   import core_v_mini_mcu_pkg::*;
@@ -374,8 +374,8 @@ module ao_peripheral_subsystem
   assign dma_trigger_slots[2] = spi_flash_rx_valid;
   assign dma_trigger_slots[3] = spi_flash_tx_ready;
   assign dma_trigger_slots[4] = i2s_rx_valid_i;
-  assign dma_trigger_slots[5] = ext_dma_slot_0_i;
-  assign dma_trigger_slots[6] = ext_dma_slot_1_i;
+  assign dma_trigger_slots[5] = ext_dma_slot_tx_i;
+  assign dma_trigger_slots[6] = ext_dma_slot_rx_i;
 
   dma #(
       .reg_req_t (reg_pkg::reg_req_t),

hw/core-v-mini-mcu/core_v_mini_mcu.sv

@@ -317,8 +317,8 @@ module core_v_mini_mcu
 
     output logic [31:0] exit_value_o,
 
-    input logic ext_dma_slot_0_i,
-    input logic ext_dma_slot_1_i
+    input logic ext_dma_slot_tx_i,
+    input logic ext_dma_slot_rx_i
 );
 
   import core_v_mini_mcu_pkg::*;
@@ -632,8 +632,8 @@ module core_v_mini_mcu
       .i2s_rx_valid_i(i2s_rx_valid),
       .ext_peripheral_slave_req_o,
       .ext_peripheral_slave_resp_i,
-      .ext_dma_slot_0_i,
-      .ext_dma_slot_1_i
+      .ext_dma_slot_tx_i,
+      .ext_dma_slot_rx_i
   );
 
   peripheral_subsystem peripheral_subsystem_i (

hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl

@@ -71,8 +71,8 @@ ${pad.core_v_mini_mcu_interface}
 
     output logic [31:0] exit_value_o,
 
-    input logic ext_dma_slot_0_i,
-    input logic ext_dma_slot_1_i
+    input logic ext_dma_slot_tx_i,
+    input logic ext_dma_slot_rx_i
 );
 
   import core_v_mini_mcu_pkg::*;
@@ -384,8 +384,8 @@ ${pad.core_v_mini_mcu_interface}
       .i2s_rx_valid_i(i2s_rx_valid),
       .ext_peripheral_slave_req_o,
       .ext_peripheral_slave_resp_i,
-      .ext_dma_slot_0_i,
-      .ext_dma_slot_1_i
+      .ext_dma_slot_tx_i,
+      .ext_dma_slot_rx_i
   );
 
   peripheral_subsystem peripheral_subsystem_i (

hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv

@@ -192,8 +192,8 @@ module xilinx_core_v_mini_mcu_wrapper
       .i2s_sck_io(i2s_sck_io),
       .i2s_ws_io(i2s_ws_io),
       .i2s_sd_io(i2s_sd_io),
-      .ext_dma_slot_0_i,
-      .ext_dma_slot_1_i,
+      .ext_dma_slot_tx_i,
+      .ext_dma_slot_rx_i,
   );
 
   assign exit_value_o = exit_value[0];

hw/ip/i2s/data/i2s.hjson

@@ -109,7 +109,7 @@
       hwext:  "true"
       hwre:   "true"
       fields: [
-        { bits: "31:0", name: "RXDATA", desc: "latest rx data if DATA_READY flag is set", hwaccess: "hrw"}
+        { bits: "31:0", name: "RXDATA", desc: "latest rx data if DATA_READY flag is set" }
       ]
     }
 

hw/ip/i2s/rtl/i2s.sv

@@ -98,7 +98,6 @@ module i2s #(
   );
 
 
-
   // Core logic
   i2s_core #(
       .MaxWordWidth(MaxWordWidth),

hw/ip_examples/iffifo/data/iffifo.hjson

@@ -2,47 +2,35 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-{ name: "iffifo",
-  clock_primary: "clk_i",
+{ name: "iffifo"
+  clock_primary: "clk_i"
   bus_interfaces: [
     { protocol: "reg_iface", direction: "device" }
   ],
-  regwidth: "32",
+  regwidth: 32
   registers: [
-    { name:     "DUMMYR",
-      desc:     "Does nothing.",
-      swaccess: "rw",
-      hwaccess: "hro",
+
+    { name:     "FIFO_OUT"
+      desc:     "Data coming from the FIFO (Fifo Output/Software RX)."
+      swaccess: "ro"
+      hwaccess: "hrw" # required for RE signal
+      hwext: "true"   # required for RE signal
+      hwre: "true"    # Used to emulate a window behaviour
       fields: [
-        { bits: "31:0", name: "DUMMY", desc: "Does nothing." }
+        { bits: "31:0", name: "FIFO_OUT", desc: "" }
       ]
-    },
-    { name:     "DUMMYW",
-      desc:     "Does nothing.",
-      swaccess: "ro",
-      hwaccess: "hrw",
+    }
+
+    { name:     "FIFO_IN"
+      desc:     "Data sent to the FIFO (Fifo Input/Software TX)."
+      hwaccess: "hro"
+      swaccess: "rw"  # required for QE signal
+      hwqe: "true"    # Used to emulate a window behaviour
       fields: [
-        { bits: "31:0", name: "DUMMY", desc: "Does nothing." }
+        { bits: "31:0", name: "FIFO_IN", desc: "" }
       ]
-    },
-    { window: {
-        name: "FIFO_OUT",
-        items: "1",
-        validbits: "32",
-        desc: '''Data coming from the FIFO (Fifo Output/Software RX)
-                  '''
-        swaccess: "ro"
-      }
-    }
-    { window: {
-        name: "FIFO_IN",
-        items: "1",
-        validbits: "32",
-        desc: '''Data sent to the FIFO (Fifo Input/Software TX)
-                  '''
-        swaccess: "wo"
-      }
     }
+
   ]
 }
 

hw/ip_examples/iffifo/iffifo.core

@@ -18,7 +18,6 @@ filesets:
     - rtl/iffifo_reg_pkg.sv
     - rtl/iffifo_reg_top.sv
     - rtl/iffifo.sv
-    - rtl/iffifo_window.sv
     file_type: systemVerilogSource
 
 targets:

hw/ip_examples/iffifo/iffifo_gen.sh

@@ -6,9 +6,3 @@ echo "Generating RTL"
 ${PYTHON} ../../vendor/pulp_platform_register_interface/vendor/lowrisc_opentitan/util/regtool.py -r -t rtl data/iffifo.hjson
 echo "Generating SW"
 ${PYTHON} ../../vendor/pulp_platform_register_interface/vendor/lowrisc_opentitan/util/regtool.py --cdefines -o ../../../sw/device/lib/drivers/iffifo/iffifo_regs.h data/iffifo.hjson
-
-echo -e ""
-echo -e ""
-echo -e ' \033[5m !!! \033[0m \033[1mIn rtl/iffifo_reg_top.sv, replace "logic [0:0] reg_steer;" by "logic [1:0] reg_steer;" \033[5m !!! \033[0m \033[0m'
-echo -e ""
-echo -e ""

hw/ip_examples/iffifo/rtl/iffifo.sv

@@ -21,31 +21,29 @@ module iffifo #(
 
   import iffifo_reg_pkg::*;
 
-  logic pop, push;
-  logic [WIDTH-1:0] fifin, fifout;
+  iffifo_reg2hw_t reg2hw;
+  iffifo_hw2reg_t hw2reg;
+
+  logic [WIDTH-1:0] fifout;
 
   assign iffifo_in_ready_o  = 1;
   assign iffifo_out_valid_o = 1;
 
-  reg_req_t [1:0] fifo_win_h2d;
-  reg_rsp_t [1:0] fifo_win_d2h;
+  assign hw2reg.fifo_out.d  = fifout + 1;
 
   iffifo_reg_top #(
       .reg_req_t(reg_req_t),
       .reg_rsp_t(reg_rsp_t)
   ) iffifo_reg_top_i (
       .clk_i,
       .rst_ni,
-      .reg2hw(),
-      .hw2reg(),
+      .reg2hw,
+      .hw2reg,
       .reg_req_i,
       .reg_rsp_o,
-      .reg_req_win_o(fifo_win_h2d),
-      .reg_rsp_win_i(fifo_win_d2h),
       .devmode_i(1'b0)
   );
 
-
   fifo_v3 #(
       .DEPTH(DEPTH),
       .DATA_WIDTH(WIDTH)
@@ -57,25 +55,10 @@ module iffifo #(
       .full_o(),
       .empty_o(),
       .usage_o(),
-      .data_i(fifin),
-      .push_i(push),
+      .data_i(reg2hw.fifo_in.q),
+      .push_i(reg2hw.fifo_in.qe),
       .data_o(fifout),
-      .pop_i(pop)
-  );
-
-  iffifo_window #(
-      .reg_req_t(reg_req_t),
-      .reg_rsp_t(reg_rsp_t)
-  ) u_window (
-      .rx_win_i  (fifo_win_h2d[0]),
-      .rx_win_o  (fifo_win_d2h[0]),
-      .tx_win_i  (fifo_win_h2d[1]),
-      .tx_win_o  (fifo_win_d2h[1]),
-      .tx_data_o (fifin),
-      .tx_be_o   (),
-      .tx_valid_o(push),
-      .rx_data_i (fifout),
-      .rx_ready_o(pop)
+      .pop_i(reg2hw.fifo_out.re)
   );
 
 endmodule : iffifo

hw/ip_examples/iffifo/rtl/iffifo_reg_pkg.sv

@@ -7,52 +7,52 @@
 package iffifo_reg_pkg;
 
   // Address widths within the block
-  parameter int BlockAw = 4;
+  parameter int BlockAw = 3;
 
   ////////////////////////////
   // Typedefs for registers //
   ////////////////////////////
 
-  typedef struct packed {logic [31:0] q;} iffifo_reg2hw_dummyr_reg_t;
-
-  typedef struct packed {logic [31:0] q;} iffifo_reg2hw_dummyw_reg_t;
+  typedef struct packed {
+    logic [31:0] q;
+    logic        re;
+  } iffifo_reg2hw_fifo_out_reg_t;
 
   typedef struct packed {
-    logic [31:0] d;
-    logic        de;
-  } iffifo_hw2reg_dummyw_reg_t;
+    logic [31:0] q;
+    logic        qe;
+  } iffifo_reg2hw_fifo_in_reg_t;
+
+  typedef struct packed {logic [31:0] d;} iffifo_hw2reg_fifo_out_reg_t;
 
   // Register -> HW type
   typedef struct packed {
-    iffifo_reg2hw_dummyr_reg_t dummyr;  // [63:32]
-    iffifo_reg2hw_dummyw_reg_t dummyw;  // [31:0]
+    iffifo_reg2hw_fifo_out_reg_t fifo_out;  // [65:33]
+    iffifo_reg2hw_fifo_in_reg_t  fifo_in;   // [32:0]
   } iffifo_reg2hw_t;
 
   // HW -> register type
   typedef struct packed {
-    iffifo_hw2reg_dummyw_reg_t dummyw;  // [32:0]
+    iffifo_hw2reg_fifo_out_reg_t fifo_out;  // [31:0]
   } iffifo_hw2reg_t;
 
   // Register offsets
-  parameter logic [BlockAw-1:0] IFFIFO_DUMMYR_OFFSET = 4'h0;
-  parameter logic [BlockAw-1:0] IFFIFO_DUMMYW_OFFSET = 4'h4;
+  parameter logic [BlockAw-1:0] IFFIFO_FIFO_OUT_OFFSET = 3'h0;
+  parameter logic [BlockAw-1:0] IFFIFO_FIFO_IN_OFFSET = 3'h4;
 
-  // Window parameters
-  parameter logic [BlockAw-1:0] IFFIFO_FIFO_OUT_OFFSET = 4'h8;
-  parameter int unsigned IFFIFO_FIFO_OUT_SIZE = 'h4;
-  parameter logic [BlockAw-1:0] IFFIFO_FIFO_IN_OFFSET = 4'hc;
-  parameter int unsigned IFFIFO_FIFO_IN_SIZE = 'h4;
+  // Reset values for hwext registers and their fields
+  parameter logic [31:0] IFFIFO_FIFO_OUT_RESVAL = 32'h0;
 
   // Register index
   typedef enum int {
-    IFFIFO_DUMMYR,
-    IFFIFO_DUMMYW
+    IFFIFO_FIFO_OUT,
+    IFFIFO_FIFO_IN
   } iffifo_id_e;
 
   // Register width information to check illegal writes
   parameter logic [3:0] IFFIFO_PERMIT[2] = '{
-      4'b1111,  // index[0] IFFIFO_DUMMYR
-      4'b1111  // index[1] IFFIFO_DUMMYW
+      4'b1111,  // index[0] IFFIFO_FIFO_OUT
+      4'b1111  // index[1] IFFIFO_FIFO_IN
   };
 
 endpackage