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minor changes
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Pierre Guillod committed Nov 20, 2023
1 parent 998bb84 commit c6eebeb
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Showing 8 changed files with 525 additions and 545 deletions.
14 changes: 3 additions & 11 deletions hw/ip/dma/data/dma.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -25,20 +25,12 @@
{ bits: "31:0", name: "PTR_OUT", desc: "Output data pointer (word aligned)" }
]
},
{ name: "DST_BCST_PTR",
desc: "Broadcast output data pointer (word aligned)",
{ name: "ADDR_BCST_PTR",
desc: "Addess/Broadcast data pointer (word aligned)",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "31:0", name: "PTR_OUT", desc: "Output data pointer (word aligned)" }
]
},
{ name: "ADDR_PTR",
desc: "Addess data pointer (word aligned)",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "31:0", name: "PTR_ADDR", desc: "Address data pointer (word aligned) - used only in Address mode" }
{ bits: "31:0", name: "PTR_ADDR", desc: "Address/Broadcast data pointer (word aligned) - used only in Address and Broadcast modes" }
]
},
{ name: "SIZE",
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4 changes: 2 additions & 2 deletions hw/ip/dma/rtl/dma.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -273,7 +273,7 @@ module dma #(
addr_ptr_reg <= '0;
end else begin
if (dma_start == 1'b1 && address_mode) begin
addr_ptr_reg <= reg2hw.addr_ptr.q;
addr_ptr_reg <= reg2hw.addr_bcst_ptr.q;
end else if (data_addr_in_gnt == 1'b1 && address_mode) begin
addr_ptr_reg <= addr_ptr_reg + 32'h4; //always continuos in 32b
end
Expand Down Expand Up @@ -312,7 +312,7 @@ module dma #(
bcst_ptr_reg <= '0;
end else begin
if (dma_start == 1'b1) begin
bcst_ptr_reg <= reg2hw.dst_bcst_ptr.q;
bcst_ptr_reg <= reg2hw.addr_bcst_ptr.q;
end else if (data_addr_in_gnt == 1'b1) begin
bcst_ptr_reg <= bcst_ptr_reg + {24'h0, reg2hw.ptr_inc.bcst_ptr_inc.q};
end
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178 changes: 104 additions & 74 deletions hw/ip/dma/rtl/dma_reg_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -13,13 +13,17 @@ package dma_reg_pkg;
// Typedefs for registers //
////////////////////////////

typedef struct packed {logic [31:0] q;} dma_reg2hw_src_ptr_reg_t;

typedef struct packed {logic [31:0] q;} dma_reg2hw_dst_ptr_reg_t;
typedef struct packed {
logic [31:0] q;
} dma_reg2hw_src_ptr_reg_t;

typedef struct packed {logic [31:0] q;} dma_reg2hw_dst_bcst_ptr_reg_t;
typedef struct packed {
logic [31:0] q;
} dma_reg2hw_dst_ptr_reg_t;

typedef struct packed {logic [31:0] q;} dma_reg2hw_addr_ptr_reg_t;
typedef struct packed {
logic [31:0] q;
} dma_reg2hw_addr_bcst_ptr_reg_t;

typedef struct packed {
logic [31:0] q;
Expand All @@ -28,47 +32,77 @@ package dma_reg_pkg;

typedef struct packed {
struct packed {
logic q;
logic re;
logic q;
logic re;
} ready;
struct packed {
logic q;
logic re;
logic q;
logic re;
} window_done;
} dma_reg2hw_status_reg_t;

typedef struct packed {
struct packed {logic [7:0] q;} src_ptr_inc;
struct packed {logic [7:0] q;} dst_ptr_inc;
struct packed {logic [7:0] q;} bcst_ptr_inc;
struct packed {
logic [7:0] q;
} src_ptr_inc;
struct packed {
logic [7:0] q;
} dst_ptr_inc;
struct packed {
logic [7:0] q;
} bcst_ptr_inc;
} dma_reg2hw_ptr_inc_reg_t;

typedef struct packed {
struct packed {logic [15:0] q;} rx_trigger_slot;
struct packed {logic [15:0] q;} tx_trigger_slot;
struct packed {
logic [15:0] q;
} rx_trigger_slot;
struct packed {
logic [15:0] q;
} tx_trigger_slot;
} dma_reg2hw_slot_reg_t;

typedef struct packed {
struct packed {logic [15:0] q;} bx_trigger_slot;
struct packed {logic [15:0] q;} dx_trigger_slot;
struct packed {
logic [15:0] q;
} bx_trigger_slot;
struct packed {
logic [15:0] q;
} dx_trigger_slot;
} dma_reg2hw_bslot_reg_t;

typedef struct packed {logic [1:0] q;} dma_reg2hw_data_type_reg_t;
typedef struct packed {
logic [1:0] q;
} dma_reg2hw_data_type_reg_t;

typedef struct packed {logic [1:0] q;} dma_reg2hw_mode_reg_t;
typedef struct packed {
logic [1:0] q;
} dma_reg2hw_mode_reg_t;

typedef struct packed {logic [31:0] q;} dma_reg2hw_window_size_reg_t;
typedef struct packed {
logic [31:0] q;
} dma_reg2hw_window_size_reg_t;

typedef struct packed {logic [31:0] q;} dma_reg2hw_window_count_reg_t;
typedef struct packed {
logic [31:0] q;
} dma_reg2hw_window_count_reg_t;

typedef struct packed {
struct packed {logic q;} transaction_done;
struct packed {logic q;} window_done;
struct packed {
logic q;
} transaction_done;
struct packed {
logic q;
} window_done;
} dma_reg2hw_interrupt_en_reg_t;

typedef struct packed {
struct packed {logic d;} ready;
struct packed {logic d;} window_done;
struct packed {
logic d;
} ready;
struct packed {
logic d;
} window_done;
} dma_hw2reg_status_reg_t;

typedef struct packed {
Expand All @@ -78,55 +112,52 @@ package dma_reg_pkg;

// Register -> HW type
typedef struct packed {
dma_reg2hw_src_ptr_reg_t src_ptr; // [322:291]
dma_reg2hw_dst_ptr_reg_t dst_ptr; // [290:259]
dma_reg2hw_dst_bcst_ptr_reg_t dst_bcst_ptr; // [258:227]
dma_reg2hw_addr_ptr_reg_t addr_ptr; // [226:195]
dma_reg2hw_size_reg_t size; // [194:162]
dma_reg2hw_status_reg_t status; // [161:158]
dma_reg2hw_ptr_inc_reg_t ptr_inc; // [157:134]
dma_reg2hw_slot_reg_t slot; // [133:102]
dma_reg2hw_bslot_reg_t bslot; // [101:70]
dma_reg2hw_data_type_reg_t data_type; // [69:68]
dma_reg2hw_mode_reg_t mode; // [67:66]
dma_reg2hw_window_size_reg_t window_size; // [65:34]
dma_reg2hw_window_count_reg_t window_count; // [33:2]
dma_reg2hw_interrupt_en_reg_t interrupt_en; // [1:0]
dma_reg2hw_src_ptr_reg_t src_ptr; // [290:259]
dma_reg2hw_dst_ptr_reg_t dst_ptr; // [258:227]
dma_reg2hw_addr_bcst_ptr_reg_t addr_bcst_ptr; // [226:195]
dma_reg2hw_size_reg_t size; // [194:162]
dma_reg2hw_status_reg_t status; // [161:158]
dma_reg2hw_ptr_inc_reg_t ptr_inc; // [157:134]
dma_reg2hw_slot_reg_t slot; // [133:102]
dma_reg2hw_bslot_reg_t bslot; // [101:70]
dma_reg2hw_data_type_reg_t data_type; // [69:68]
dma_reg2hw_mode_reg_t mode; // [67:66]
dma_reg2hw_window_size_reg_t window_size; // [65:34]
dma_reg2hw_window_count_reg_t window_count; // [33:2]
dma_reg2hw_interrupt_en_reg_t interrupt_en; // [1:0]
} dma_reg2hw_t;

// HW -> register type
typedef struct packed {
dma_hw2reg_status_reg_t status; // [34:33]
dma_hw2reg_window_count_reg_t window_count; // [32:0]
dma_hw2reg_status_reg_t status; // [34:33]
dma_hw2reg_window_count_reg_t window_count; // [32:0]
} dma_hw2reg_t;

// Register offsets
parameter logic [BlockAw-1:0] DMA_SRC_PTR_OFFSET = 6'h0;
parameter logic [BlockAw-1:0] DMA_DST_PTR_OFFSET = 6'h4;
parameter logic [BlockAw-1:0] DMA_DST_BCST_PTR_OFFSET = 6'h8;
parameter logic [BlockAw-1:0] DMA_ADDR_PTR_OFFSET = 6'hc;
parameter logic [BlockAw-1:0] DMA_SIZE_OFFSET = 6'h10;
parameter logic [BlockAw-1:0] DMA_STATUS_OFFSET = 6'h14;
parameter logic [BlockAw-1:0] DMA_PTR_INC_OFFSET = 6'h18;
parameter logic [BlockAw-1:0] DMA_SLOT_OFFSET = 6'h1c;
parameter logic [BlockAw-1:0] DMA_BSLOT_OFFSET = 6'h20;
parameter logic [BlockAw-1:0] DMA_DATA_TYPE_OFFSET = 6'h24;
parameter logic [BlockAw-1:0] DMA_MODE_OFFSET = 6'h28;
parameter logic [BlockAw-1:0] DMA_WINDOW_SIZE_OFFSET = 6'h2c;
parameter logic [BlockAw-1:0] DMA_WINDOW_COUNT_OFFSET = 6'h30;
parameter logic [BlockAw-1:0] DMA_INTERRUPT_EN_OFFSET = 6'h34;
parameter logic [BlockAw-1:0] DMA_SRC_PTR_OFFSET = 6'h 0;
parameter logic [BlockAw-1:0] DMA_DST_PTR_OFFSET = 6'h 4;
parameter logic [BlockAw-1:0] DMA_ADDR_BCST_PTR_OFFSET = 6'h 8;
parameter logic [BlockAw-1:0] DMA_SIZE_OFFSET = 6'h c;
parameter logic [BlockAw-1:0] DMA_STATUS_OFFSET = 6'h 10;
parameter logic [BlockAw-1:0] DMA_PTR_INC_OFFSET = 6'h 14;
parameter logic [BlockAw-1:0] DMA_SLOT_OFFSET = 6'h 18;
parameter logic [BlockAw-1:0] DMA_BSLOT_OFFSET = 6'h 1c;
parameter logic [BlockAw-1:0] DMA_DATA_TYPE_OFFSET = 6'h 20;
parameter logic [BlockAw-1:0] DMA_MODE_OFFSET = 6'h 24;
parameter logic [BlockAw-1:0] DMA_WINDOW_SIZE_OFFSET = 6'h 28;
parameter logic [BlockAw-1:0] DMA_WINDOW_COUNT_OFFSET = 6'h 2c;
parameter logic [BlockAw-1:0] DMA_INTERRUPT_EN_OFFSET = 6'h 30;

// Reset values for hwext registers and their fields
parameter logic [1:0] DMA_STATUS_RESVAL = 2'h1;
parameter logic [0:0] DMA_STATUS_READY_RESVAL = 1'h1;
parameter logic [0:0] DMA_STATUS_WINDOW_DONE_RESVAL = 1'h0;
parameter logic [1:0] DMA_STATUS_RESVAL = 2'h 1;
parameter logic [0:0] DMA_STATUS_READY_RESVAL = 1'h 1;
parameter logic [0:0] DMA_STATUS_WINDOW_DONE_RESVAL = 1'h 0;

// Register index
typedef enum int {
DMA_SRC_PTR,
DMA_DST_PTR,
DMA_DST_BCST_PTR,
DMA_ADDR_PTR,
DMA_ADDR_BCST_PTR,
DMA_SIZE,
DMA_STATUS,
DMA_PTR_INC,
Expand All @@ -140,21 +171,20 @@ package dma_reg_pkg;
} dma_id_e;

// Register width information to check illegal writes
parameter logic [3:0] DMA_PERMIT[14] = '{
4'b1111, // index[ 0] DMA_SRC_PTR
4'b1111, // index[ 1] DMA_DST_PTR
4'b1111, // index[ 2] DMA_DST_BCST_PTR
4'b1111, // index[ 3] DMA_ADDR_PTR
4'b1111, // index[ 4] DMA_SIZE
4'b0001, // index[ 5] DMA_STATUS
4'b0111, // index[ 6] DMA_PTR_INC
4'b1111, // index[ 7] DMA_SLOT
4'b1111, // index[ 8] DMA_BSLOT
4'b0001, // index[ 9] DMA_DATA_TYPE
4'b0001, // index[10] DMA_MODE
4'b1111, // index[11] DMA_WINDOW_SIZE
4'b1111, // index[12] DMA_WINDOW_COUNT
4'b0001 // index[13] DMA_INTERRUPT_EN
parameter logic [3:0] DMA_PERMIT [13] = '{
4'b 1111, // index[ 0] DMA_SRC_PTR
4'b 1111, // index[ 1] DMA_DST_PTR
4'b 1111, // index[ 2] DMA_ADDR_BCST_PTR
4'b 1111, // index[ 3] DMA_SIZE
4'b 0001, // index[ 4] DMA_STATUS
4'b 0111, // index[ 5] DMA_PTR_INC
4'b 1111, // index[ 6] DMA_SLOT
4'b 1111, // index[ 7] DMA_BSLOT
4'b 0001, // index[ 8] DMA_DATA_TYPE
4'b 0001, // index[ 9] DMA_MODE
4'b 1111, // index[10] DMA_WINDOW_SIZE
4'b 1111, // index[11] DMA_WINDOW_COUNT
4'b 0001 // index[12] DMA_INTERRUPT_EN
};

endpackage
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