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Test uses STP
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gussmith23 committed Dec 14, 2023
1 parent eb753b1 commit c3ec67a
Showing 1 changed file with 2 additions and 28 deletions.
30 changes: 2 additions & 28 deletions integration_tests/lakeroad/xilinx_muladd_3_stage_signed_18_bit.sv
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// RUN: outfile=$(mktemp)
// RUN: (racket $LAKEROAD_DIR/bin/main.rkt \
// RUN: --solver cvc5 \
// RUN: --solver stp \
// RUN: --verilog-module-filepath %s \
// RUN: --architecture xilinx-ultrascale-plus \
// RUN: --template dsp \
Expand All @@ -19,32 +19,6 @@
// RUN: > $outfile \
// RUN: 2>&1
// RUN: FileCheck %s < $outfile
// if [ -z ${LAKEROAD_PRIVATE_DIR+x} ]; then \
// echo "Warning: LAKEROAD_PRIVATE_DIR is not set. Skipping simulation."; \
// exit 0; \
// else \
// python3 $LAKEROAD_DIR/bin/simulate_with_verilator.py \
// --test_module_name test_module \
// --ground_truth_module_name top \
// --max_num_tests=10000 \
// --verilog_filepath $outfile \
// --verilog_filepath %s \
// --clock_name clk \
// --initiation_interval 3 \
// --output_signal out:18 \
// --input_signal a:18 \
// --input_signal b:18 \
// --input_signal c:18 \
// --verilator_include_dir "$LAKEROAD_PRIVATE_DIR/DSP48E2/" \
// --verilator_extra_arg='-DXIL_XECLIB' \
// --verilator_extra_arg='-Wno-UNOPTFLAT' \
// --verilator_extra_arg='-Wno-LATCH' \
// --verilator_extra_arg='-Wno-WIDTH' \
// --verilator_extra_arg='-Wno-STMTDLY' \
// --verilator_extra_arg='-Wno-CASEX' \
// --verilator_extra_arg='-Wno-TIMESCALEMOD' \
// --verilator_extra_arg='-Wno-PINMISSING'; \
// fi

(* use_dsp = "yes" *) module top(
input signed [17:0] a,
Expand All @@ -67,4 +41,4 @@
assign out = stage2;
endmodule

// CHECK: Synthesis Timeout
// CHECK: Synthesis failed

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