AI HW Acceleration

[jzhou1318]

Before submitting your Pull Request, please ensure that you have carefully reviewed and completed all items on this checklist.

1. Content

   • The chapter content is complete and covers the topic in detail.
   • All technical terms are well-defined and explained.
   • Any code snippets or algorithms are well-documented and tested.
   • The chapter follows a logical flow and structure.

2. References & Citations

   • All references are correctly listed at the end of the chapter.
   • In-text citations are used appropriately and match the references.
   • All figures, tables, and images have proper sources and are cited correctly.

3. Quarto Website Rendering

   • The chapter has been locally built and tested using Quarto.
   • All images, figures, and tables render properly without any glitches.
   • All images have a source or they are properly linked to external sites.
   • Any interactive elements or widgets work as intended.
   • The chapter's formatting is consistent with the rest of the book.

4. Grammar & Style

   • The chapter has been proofread for grammar and spelling errors.
   • The writing style is consistent with the rest of the book.
   • Any jargon is clearly explained or avoided where possible.

5. Collaboration

   • All group members have reviewed and approved the chapter.
   • Any feedback from previous reviews or discussions has been addressed.

6. Miscellaneous

   • All external links (if any) are working and lead to the intended destinations.
   • If datasets or external resources are used, they are properly credited and linked.
   • Any necessary permissions for reused content have been obtained.

7. Final Steps

   • The chapter is pushed to the correct branch on the repository.
   • The Pull Request is made with a clear title and description.
   • The Pull Request includes any necessary labels or tags.
   • The Pull Request mentions any stakeholders or reviewers who should take a look.

[AditiR-42]

Typo: Wafer-scale AI

[profvjreddi]

Thank you, fixed.

[arnaumarin]

Thanks!

[AditiR-42]

This example is a bit difficult to follow. It would be nice to have a step by step explanation of why an FPGA-based AI accelerator should be simulated using Verilog (what exactly about Verilog makes it well-suited for this type of accelerator?), as well as why it should be synthesized into a Gem5 model (what specifically about Gem5 makes it optimal for this task?)

[profvjreddi]

Is this helpful @AditiR-42

For example, an FPGA-based AI accelerator design could be simulated using Verilog hardware description language and synthesized into a Gem5 model. Verilog is well-suited for describing the digital logic and interconnects that make up the accelerator architecture. Using Verilog allows the designer to specify the datapaths, control logic, on-chip memories, and other components that will be implemented in the FPGA fabric. Once the Verilog design is complete, it can be synthesized into a model that simulates the behavior of the hardware, such as using the Gem5 simulator. Gem5 is useful for this task because it allows modeling of full systems including processors, caches, buses, and custom accelerators. Gem5 supports interfacing Verilog models of hardware to the simulation, enabling unified system modeling.

The synthesized FPGA accelerator model could then have ML workloads simulated using TVM compiled onto it within the Gem5 environment for unified modeling. TVM allows optimized compilation of ML models onto heterogeneous hardware like FPGAs. Running TVM-compiled workloads on the accelerator within the Gem5 simulation provides an integrated way to validate and refine the hardware design, software stack, and system integration before ever needing to physically realize the accelerator on a real FPGA.

[profvjreddi]

Hope that works, updated it in the text.

[arnaumarin]

Looks good. Thanks for addressing the typo!

[gnodipac886]

added more references to the sections that I was responsible for (challenges and solutions)

[profvjreddi]

Thank you folks!

…

On Mon, Nov 13, 2023 at 2:43 PM gnodipac886 ***@***.***> wrote: added more references to the sections that I was responsible for (challenges and solutions) — Reply to this email directly, view it on GitHub <#53 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ABT6DFHEIR277A7XR7NHVTTYEJZ4LAVCNFSM6AAAAAA7C5SPIOVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTQMBYHEYTQMJYGA> . You are receiving this because you commented.Message ID: ***@***.***>

-- Vijay Janapa Reddi, Ph. D. | John L. Loeb Associate Professor of Engineering and Applied Sciences | John A. Paulson School of Engineering and Applied Sciences | Science and Engineering Complex (SEC) | 150 Western Ave, Room #5.305 | Boston, MA 02134 | Harvard University | Email ***@***.***> | Website <http://scholar.harvard.edu/vijay-janapa-reddi> | Google Scholar <https://scholar.google.com/citations?hl=en&user=gy4UVGcAAAAJ&view_op=list_works&sortby=pubdate> | Edge Computing Lab <https://edge.seas.harvard.edu> | Schedule a Meeting <https://scholar.harvard.edu/vijay-janapa-reddi/schedule> | Admin <https://scholar.harvard.edu/vijay-janapa-reddi/contact> |

[mpstewart1]

Really great job on this chapter!