Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add SystemRDL & PeakRDL tools #242

Open
wants to merge 1 commit into
base: develop
Choose a base branch
from
Open
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
51 changes: 51 additions & 0 deletions content/items/peakrdl.md
Original file line number Diff line number Diff line change
@@ -0,0 +1,51 @@
---
title: "PeakRDL"
description: "Control & Status register (CSR) automation toolchain"
authors:
- Alex Mykyta
links:
gh: "SystemRDL/PeakRDL"
docs: "https://peakrdl.readthedocs.io"
tags:
- SystemRDL
- code-generator
- Python
- configuration-register
- csr
- verilog
- systemverilog
- documentation
- UVM-reg
- RTL
- abstract
categories:
- "Tools:CSR Automation"
licenses:
- GPL-3.0
active:
from: 2018
talk: 241
---

PeakRDL is a free and open-source control & status register (CSR) automation
toolchain. This project provides a command-line tool that unifies many aspects of register automation centered around the SystemRDL register description language.

This tool can:

* Process SystemRDL 2.0 register descriptions.
* Import & export IP-XACT XML.
* Generate synthesizable SystemVerilog RTL register blocks using APB, AXI4-Lite, Avalon, and other interfaces.
* Create rich and dynamic HTML documentation.
* Build a UVM register model abstraction layer.
* Generate C headers for software.
* ... or be extended with your own plugin to generate other outputs

## References

- [SystemRDL Compiler]({{< ref "/items/systemrdl-compiler" >}} "SystemRDL Compiler")
- [PeakRDL-cheader](https://github.com/SystemRDL/PeakRDL-cheader)
- [PeakRDL-html](https://github.com/SystemRDL/PeakRDL-html)
- [PeakRDL-ipxact](https://github.com/SystemRDL/PeakRDL-ipxact)
- [PeakRDL-regblock](https://github.com/SystemRDL/PeakRDL-regblock)
- [PeakRDL-systemrdl](https://github.com/SystemRDL/PeakRDL-systemrdl)
- [PeakRDL-uvm](https://github.com/SystemRDL/PeakRDL-uvm)
38 changes: 38 additions & 0 deletions content/items/systemrdl-compiler.md
Original file line number Diff line number Diff line change
@@ -0,0 +1,38 @@
---
title: "SystemRDL Compiler"
description: "SystemRDL language compiler front-end"
authors:
- Alex Mykyta
links:
gh: "SystemRDL/systemrdl-compiler"
docs: "https://systemrdl-compiler.readthedocs.io"
tags:
- SystemRDL
- language-model
- parser
- compiler
- code-generator
- Python
- configuration-register
- csr
categories:
- "Tools:CSR Automation"
licenses:
- MIT
active:
from: 2017
talk: 241
---

SystemRDL is a domain specific language used to describe control/status
registers (CSR) that define a hardware/software boundary for hardware
peripherals. By describing the structure of a CSR in SystemRDL, one can create a single source of truth specification for CSR automation and code generation.

The `systemrdl-compiler` project implements a generic compiler front-end for
Accellera's [SystemRDL 2.0](http://accellera.org/downloads/standards/systemrdl)
register description language. The goal of this project is to provide a free and
open compiler that lowers the barrier to entry to using an industry standard
register description language.

By providing an elaborated register model that is easy to traverse and query,
it should be far easier to write custom register space view generators.
Binary file added static/logos/peakrdl.png
Loading
Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.
Binary file added static/logos/systemrdl-compiler.png
Loading
Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.