Adding autoname and opt_clean -purge Yosys pass to synth.tcl

The [`opt_clean` pass](https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/opt_clean.html)
removes unused items, the `-purge` is needed to remove the duplicate private
names.

The [`autoname` pass](https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/autoname.html)
converts the internal `_<random number>_` names into something which is a lot
more readable (as it is based on the input and outputs).

Before;
```
  (* src = "adders/top_ff.sv:22.3-23.13" *)
  sky130_fd_sc_hd__dfxtp_1 _47_ (
    .CLK(clk),
    .D(a[8]),
    .Q(a_[8])
  );
  (* src = "adders/top_ff.sv:28.3-29.13" *)
  sky130_fd_sc_hd__dfxtp_1 _48_ (
    .CLK(clk),
    .D(i_[0]),
    .Q(x[0])
  );
```

After;
```
  (* src = "adders/top_ff.sv:22.3-23.13" *)
  sky130_fd_sc_hd__dfxtp_1 \a__$_DFF_P__Q  (
    .CLK(clk),
    .D(a[8]),
    .Q(a_[8])
  );
  (* src = "top_ff.sv:28.3-29.13" *)
  sky130_fd_sc_hd__dfxtp_1 \x_$_DFF_P__Q_5  (
    .CLK(clk),
    .D(i_[0]),
    .Q(x[0])
  );
```

Signed-off-by: Tim Ansell <[email protected]>

synthesis/synth.tcl

@@ -46,8 +46,22 @@ hierarchy -check -top $top
 yosys proc -nomux
 yosys proc_mux
 yosys flatten
+
+# Remove internal only aliases for public nets and then give created instances
+# useful names. At this stage it is mainly flipflops created by the `proc`
+# pass.
+yosys opt_clean -purge
+yosys autoname
+
 yosys synth -top $top
 
+# Remove internal only aliases for public nets and then give created instances
+# useful names. At this stage it is all the other synthesizable constructs.
+# This should be done before techmapping where things can be converted
+# dramatically and having useful names is helpful for debugging.
+yosys opt_clean -purge
+yosys autoname
+
 # mapping to liberty
 set liberty $::env(LIBERTY)
 dfflibmap -liberty $liberty
@@ -58,6 +72,12 @@ if { [info exists ::env(CLOCK_PERIOD) ] } {
   abc -liberty $liberty -dff -g aig
 }
 
+# Remove internal only aliases for public nets and then give created instances
+# useful names. At this stage it is anything generated by the techmapping
+# passes.
+yosys opt_clean -purge
+yosys autoname
+
 # write synthesized design
 set output $::env(OUTPUT)
 write_verilog $output