Merge pull request #208 from hdl/delete_print_cells

Add a line to synth.tcl to remove Yosys $print cells.

synthesis/synth.tcl

@@ -52,6 +52,11 @@ yosys proc -nomux
 yosys proc_mux
 yosys flatten
 
+# Remove $print cells.  These cells represent Verilog $display() tasks.
+# Some place and route tools cannot handle these in the output Verilog,
+# so remove them here.
+yosys delete {*/t:$print}
+
 # Remove internal only aliases for public nets and then give created instances
 # useful names. At this stage it is mainly flipflops created by the `proc`
 # pass.