Temp7

hdl · Nov 1, 2023 · 4228f1d · 4228f1d
1 parent 0a303b1
commit 4228f1d
Show file tree

Hide file tree

Showing 3 changed files with 94 additions and 2 deletions.
diff --git a/dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26_rvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26_rvt-cells.bzl
@@ -21,3 +21,49 @@ asap7_cells_files(
     vt = "rvt",
 )
 
+open_road_pdk_configuration(
+    name = "open_road-asap7-sc6t_rev26_rvt",
+    cell_site = "asap7sc7p5t",
+    cts_buffer_cell = "BUFx4_ASAP7_75t_R",
+    do_not_use_cell_list = [
+        "*x1_ASAP7*",
+        "*x1p*_ASAP7*",
+        "*xp*_ASAP7*",
+        "SDF*",
+        "ICG*",
+        "DFFH*",
+    ],
+    endcap_cell = "TAPCELL_ASAP7_75t_R",
+    fill_cells = [
+        "FILLERxp5_ASAP7_75t_R",
+        "DECAPx1_ASAP7_75t_R",
+        "DECAPx2_ASAP7_75t_R",
+        "DECAPx4_ASAP7_75t_R",
+        "DECAPx6_ASAP7_75t_R",
+        "DECAPx10_ASAP7_75t_R",
+    ],
+    global_placement_cell_pad = 2,
+    global_routing_clock_layers = "M2-M7",
+    global_routing_layer_adjustments = {
+        "M2": "0.5",
+        "M3": "0.5",
+        "M4": "0.5",
+        "M5": "0.5",
+        "M6": "0.5",
+        "M7": "0.5",
+    },
+    global_routing_signal_layers = "M2-M7",
+    klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt",
+    pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config.pdn",
+    pin_horizontal_metal_layer = "M4",
+    pin_vertical_metal_layer = "M5",
+    rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl",
+    tap_cell = "TAPCELL_ASAP7_75t_R",
+    tapcell_distance = 25,
+    tie_high_port = "TIEHIx1_ASAP7_75t_R/H",
+    tie_low_port = "TIELOx1_ASAP7_75t_R/L",
+    tie_separation = 0,
+    tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl",
+    wire_rc_clock_metal_layer = "M5",
+    wire_rc_signal_metal_layer = "M2",
+)
diff --git a/dependency_support/org_theopenroadproject_asap7/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7/bundled.BUILD.bazel
@@ -89,6 +89,52 @@ asap7_cells_files(
     vt = "rvt",
 )
 
+open_road_pdk_configuration(
+    name = "open_road-asap7-sc6t_rev26_rvt",
+    cell_site = "asap7sc7p5t",
+    cts_buffer_cell = "BUFx4_ASAP7_75t_R",
+    do_not_use_cell_list = [
+        "*x1_ASAP7*",
+        "*x1p*_ASAP7*",
+        "*xp*_ASAP7*",
+        "SDF*",
+        "ICG*",
+        "DFFH*",
+    ],
+    endcap_cell = "TAPCELL_ASAP7_75t_R",
+    fill_cells = [
+        "FILLERxp5_ASAP7_75t_R",
+        "DECAPx1_ASAP7_75t_R",
+        "DECAPx2_ASAP7_75t_R",
+        "DECAPx4_ASAP7_75t_R",
+        "DECAPx6_ASAP7_75t_R",
+        "DECAPx10_ASAP7_75t_R",
+    ],
+    global_placement_cell_pad = 2,
+    global_routing_clock_layers = "M2-M7",
+    global_routing_layer_adjustments = {
+        "M2": "0.5",
+        "M3": "0.5",
+        "M4": "0.5",
+        "M5": "0.5",
+        "M6": "0.5",
+        "M7": "0.5",
+    },
+    global_routing_signal_layers = "M2-M7",
+    klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt",
+    pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config.pdn",
+    pin_horizontal_metal_layer = "M4",
+    pin_vertical_metal_layer = "M5",
+    rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl",
+    tap_cell = "TAPCELL_ASAP7_75t_R",
+    tapcell_distance = 25,
+    tie_high_port = "TIEHIx1_ASAP7_75t_R/H",
+    tie_low_port = "TIELOx1_ASAP7_75t_R/L",
+    tie_separation = 0,
+    tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl",
+    wire_rc_clock_metal_layer = "M5",
+    wire_rc_signal_metal_layer = "M2",
+)
 
 # From asap7-sc6t_rev26_slvt-cells.bzl
 # ASAP7 "rev 26" 6 track standard cell library using super-low VT transistors
@@ -342,7 +388,7 @@ asap7_cell_library(
     default_corner_delay_model = "ccs",
     default_corner_swing = "SS",
     openroad_configuration = ":open_road-asap7-sc7p5t_rev27_rvt_4x",
-    tech_lef = ":asap7-cells-sc7p5t_rev27_4x-tech-lef",
+    tech_lef = ":asap7-misc-sc7p5t_rev27_4x-lef",
     visibility = [
         "//visibility:public",
     ]

diff --git a/synthesis/tests/BUILD b/synthesis/tests/BUILD
@@ -56,7 +56,7 @@ synthesize_rtl(
 
 run_opensta(
     name = "verilog_counter-synth_sta",
-    synth_target = ":verilog_counter_synth",
+    synth_target = ":verilog_counter-synth",
 )
 
 place_and_route(