reformat bzl

Signed-off-by: Ethan Mahintorabi <[email protected]>
hdl · Nov 2, 2024 · 8548293 · 8548293
1 parent 2b372e7
commit 8548293
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/synthesis/build_defs.bzl b/synthesis/build_defs.bzl
@@ -221,7 +221,7 @@ def _synthesize_design_impl(ctx):
                 data = [],
                 deps = [],
                 tags = [],
-            )]
+            )],
         ),
     ]
 

diff --git a/verilog/defs.bzl b/verilog/defs.bzl
@@ -3,12 +3,12 @@
 load(
     ":providers.bzl",
     _VerilogInfo = "VerilogInfo",
-    _verilog_library = "verilog_library",
     _make_dag_entry = "make_dag_entry",
     _make_verilog_info = "make_verilog_info",
+    _verilog_library = "verilog_library",
 )
 
 VerilogInfo = _VerilogInfo
 verilog_library = _verilog_library
 make_dag_entry = _make_dag_entry
-make_verilog_info = _make_verilog_info
+make_verilog_info = _make_verilog_info
-Original file line number
+Diff line change
@@ Expand Up / @@ -221,7 +221,7 @@ def _synthesize_design_impl(ctx): @@
                     data = [],
                     deps = [],
                     tags = [],
-                )]
+                )],
             ),
         ]
@@ Expand Down @@