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Rework for the ASAP7 repo reorganization.
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Signed-off-by: Tim 'mithro' Ansell <[email protected]>
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@mithro
mithro committed Nov 8, 2023
1 parent 2b6e962 commit f2c1c44
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Showing 34 changed files with 1,272 additions and 1,358 deletions.
3 changes: 2 additions & 1 deletion WORKSPACE
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Original file line number Diff line number Diff line change
Expand Up @@ -93,12 +93,13 @@ llvm_toolchain(
maybe(
http_archive,
name = "rules_7zip",
sha256 = "fd9e99f6ccb9e946755f9bc444abefbdd1eedb32c372c56dcacc7eb486aed178",
strip_prefix = "rules_7zip-e00b15d3cb76b78ddc1c15e7426eb1d1b7ddaa3e",
urls = ["https://github.com/zaucy/rules_7zip/archive/e00b15d3cb76b78ddc1c15e7426eb1d1b7ddaa3e.zip"],
sha256 = "fd9e99f6ccb9e946755f9bc444abefbdd1eedb32c372c56dcacc7eb486aed178",
)

load("@rules_7zip//:setup.bzl", "setup_7zip")

setup_7zip()

maybe(
Expand Down
2 changes: 1 addition & 1 deletion dependency_support/com_icarus_iverilog/com_icarus_iverilog.bzl
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@ def com_icarus_iverilog():
http_archive,
name = "com_icarus_iverilog",
urls = [
"https://github.com/steveicarus/iverilog/archive/v12_0.tar.gz",
"https://github.com/steveicarus/iverilog/archive/v12_0.tar.gz",
],
strip_prefix = "iverilog-12_0",
sha256 = "a68cb1ef7c017ef090ebedb2bc3e39ef90ecc70a3400afb4aa94303bc3beaa7d",
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4 changes: 4 additions & 0 deletions dependency_support/dependency_support.bzl
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Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,8 @@ load("@rules_hdl//dependency_support/org_sourceware_libffi:org_sourceware_libffi
load("@rules_hdl//dependency_support/org_swig:org_swig.bzl", "org_swig")
load("@rules_hdl//dependency_support/org_theopenroadproject:org_theopenroadproject.bzl", "org_theopenroadproject")
load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:org_theopenroadproject_asap7_pdk_r1p7.bzl", "org_theopenroadproject_asap7_pdk_r1p7")
load("@rules_hdl//dependency_support/org_theopenroadproject_asap7sc6t_26:org_theopenroadproject_asap7sc6t_26.bzl", "org_theopenroadproject_asap7sc6t_26")
load("@rules_hdl//dependency_support/org_theopenroadproject_asap7sc7p5t_27:org_theopenroadproject_asap7sc7p5t_27.bzl", "org_theopenroadproject_asap7sc7p5t_27")
load("@rules_hdl//dependency_support/org_theopenroadproject_asap7sc7p5t_28:org_theopenroadproject_asap7sc7p5t_28.bzl", "org_theopenroadproject_asap7sc7p5t_28")
load("@rules_hdl//dependency_support/pybind11:pybind11.bzl", "pybind11")
load("@rules_hdl//dependency_support/tk_tcl:tk_tcl.bzl", "tk_tcl")
Expand Down Expand Up @@ -105,6 +107,8 @@ def dependency_support():
org_swig()
org_theopenroadproject()
org_theopenroadproject_asap7_pdk_r1p7()
org_theopenroadproject_asap7sc6t_26()
org_theopenroadproject_asap7sc7p5t_27()
org_theopenroadproject_asap7sc7p5t_28()
pybind11()
tk_tcl()
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96 changes: 0 additions & 96 deletions dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_rvt-cells.bzl
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This file was deleted.

100 changes: 43 additions & 57 deletions dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl
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Original file line number Diff line number Diff line change
Expand Up @@ -3,65 +3,81 @@
load("@rules_hdl//pdk:build_defs.bzl", "CornerInfo", "StandardCellInfo")
load("@rules_hdl//pdk:open_road_configuration.bzl", "OpenRoadPdkInfo")

<<<<<<< HEAD
def asap7_srams_files(name = None, rev = None, tracks = None, has_gds = True):
"""Generate ASAP7 sram's filegroup targets (asap7-cells-XXX).
Args:
name: Macro instance name.
rev: ASAP7 revision ("26" / "27" / "28").
tracks: Number of tracks ("7p5t", "6t").
has_gds: SRAM have GDS layouts.
"""

def asap7_srams_files(name=None, rev=None, tracks=None, has_gds=True):
if rev not in ["26", "27", "28"]:
fail("Invalid rev {}".format(repr(rev)))
if tracks not in ["7p5t", "6t"]:
fail("Invalid rev {}".format(repr(tracks)))

args = {
'rev': str(rev),
'tracks': str(tracks),
"rev": str(rev),
"tracks": str(tracks),
}

# Layouts for GDS generation
# ------------------------------------------------------------------------
if has_gds:
native.filegroup(
name = "asap7-srams-sc{tracks}_rev{rev}-gds".format(**args),
srcs = native.glob(["asap7sc{tracks}_{rev}/GDS/asap7sc{tracks}_{rev}*_SRAM_*.gds".format(**args)]),
srcs = native.glob(["GDS/asap7sc{tracks}_{rev}*_SRAM_*.gds".format(**args)]),
)

# Timing information (in compressed Liberty format) for synthesis and static
# timing analysis (STA).
# ------------------------------------------------------------------------
native.filegroup(
name = "asap7-srams-sc{tracks}_rev{rev}-libgz".format(**args),
srcs = native.glob(["asap7sc{tracks}_{rev}/LIB/CCS/*SRAM*.lib.gz".format(**args)]),
name = "asap7-srams-sc{tracks}_rev{rev}-lib7z".format(**args),
srcs = native.glob(["LIB/CCS/*SRAM*.lib.7z".format(**args)]),
)

# Verilog models for digital simulation and logical equivalence
# ------------------------------------------------------------------------
native.filegroup(
name = "asap7-srams-sc{tracks}_rev{rev}-v".format(**args),
srcs = native.glob(["asap7sc{tracks}_{rev}/Verilog/asap7sc{tracks}_*_SRAM_*.v".format(**args)]),
srcs = native.glob(["Verilog/asap7sc{tracks}_*_SRAM_*.v".format(**args)]),
)

# CDL models for LVS checking
# ------------------------------------------------------------------------
native.filegroup(
name = "asap7-srams-sc{tracks}_rev{rev}-lvs".format(**args),
srcs = ["asap7sc{tracks}_{rev}/CDL/LVS/asap7sc{tracks}_{rev}_*SRAM*.cdl".format(**args)],
srcs = ["CDL/LVS/asap7sc{tracks}_{rev}_*SRAM*.cdl".format(**args)],
)

# CDL models for Spice simulation
# ------------------------------------------------------------------------
native.filegroup(
name = "asap7-srams-sc{tracks}_rev{rev}-spice".format(**args),
srcs = ["asap7sc{tracks}_{rev}/CDL/xAct3D_extracted/asap7sc{tracks}_{rev}_*SRAM*.sp".format(**args)],
srcs = ["CDL/xAct3D_extracted/asap7sc{tracks}_{rev}_*SRAM*.sp".format(**args)],
)

# Place and route
# ------------------------------------------------------------------------
native.filegroup(
name = "asap7-srams-sc{tracks}_rev{rev}-lef".format(**args),
srcs = ["asap7sc{tracks}_{rev}/LEF/asap7sc{tracks}_{rev}*_SRAM_*.lef".format(**args)],
srcs = ["LEF/asap7sc{tracks}_{rev}*_SRAM_*.lef".format(**args)],
)

def asap7_cells_files(name = None, rev = None, tracks = None, vt = None, has_gds = True):
"""Generate ASAP7 cell's filegroup targets (asap7-cells-XXX).
Args:
name: Macro instance name.
rev: ASAP7 revision ("26" / "27" / "28").
tracks: Number of tracks ("7p5t", "6t").
vt: VT type ("rvt", "lvt", "slvt").
has_gds: Cells have GDS layouts.
"""

def asap7_cells_files(name=None, rev=None, tracks=None, vt=None, has_gds=True):
if rev not in ["26", "27", "28"]:
fail("Invalid rev {}".format(repr(rev)))
if tracks not in ["7p5t", "6t"]:
Expand All @@ -70,64 +86,64 @@ def asap7_cells_files(name=None, rev=None, tracks=None, vt=None, has_gds=True):
fail("Invalid vt {}".format(repr(vt)))

args = {
'rev': rev,
'tracks': tracks,
'vt_long': vt,
'vt_upper': vt.upper(),
'vt_short': {'rvt': 'R', 'lvt': 'L', 'slvt': 'SL'}[vt],
"rev": rev,
"tracks": tracks,
"vt_long": vt,
"vt_upper": vt.upper(),
"vt_short": {"rvt": "R", "lvt": "L", "slvt": "SL"}[vt],
}

# Layouts for GDS generation
# ------------------------------------------------------------------------
if has_gds:
native.filegroup(
name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-gds".format(**args),
srcs = native.glob(["asap7sc{tracks}_{rev}/GDS/asap7sc{tracks}_{rev}_{vt_short}*.gds".format(**args)]),
srcs = native.glob(["GDS/asap7sc{tracks}_{rev}_{vt_short}*.gds".format(**args)]),
)

# Timing information (in compressed Liberty format) for synthesis and static
# timing analysis (STA).
# ------------------------------------------------------------------------
native.filegroup(
name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-libgz".format(**args),
srcs = native.glob(["asap7sc{tracks}_{rev}/LIB/CCS/*_{vt_upper}_*.lib.gz".format(**args)]),
name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lib7z".format(**args),
srcs = native.glob(["LIB/CCS/*_{vt_upper}_*.lib.7z".format(**args)]),
)

# Verilog models for digital simulation and logical equivalence
# ------------------------------------------------------------------------
native.filegroup(
name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-v".format(**args),
srcs = native.glob(["asap7sc{tracks}_{rev}/Verilog/asap7sc{tracks}_*_{vt_upper}_*.v".format(**args)]),
srcs = native.glob(["Verilog/asap7sc{tracks}_*_{vt_upper}_*.v".format(**args)]),
)

# CDL models for LVS checking
# ------------------------------------------------------------------------
native.filegroup(
name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lvs".format(**args),
srcs = native.glob(["asap7sc{tracks}_{rev}/CDL/LVS/asap7sc{tracks}_{rev}_{vt_short}.cdl".format(**args)]),
srcs = native.glob(["CDL/LVS/asap7sc{tracks}_{rev}_{vt_short}.cdl".format(**args)]),
)

# CDL models for Spice simulation
# ------------------------------------------------------------------------
native.filegroup(
name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-spice".format(**args),
srcs = native.glob(["asap7sc{tracks}_{rev}/CDL/xAct3D_extracted/asap7sc{tracks}_{rev}_{vt_short}.sp".format(**args)]),
srcs = native.glob(["CDL/xAct3D_extracted/asap7sc{tracks}_{rev}_{vt_short}.sp".format(**args)]),
)

# Place and route
# ------------------------------------------------------------------------
native.filegroup(
name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lef".format(**args),
srcs = native.glob(["asap7sc{tracks}_{rev}/LEF/asap7sc{tracks}_{rev}_{vt_short}_1x*.lef".format(**args)]),
srcs = native.glob(["LEF/asap7sc{tracks}_{rev}_{vt_short}_1x*.lef".format(**args)]),
)

# Library configuration
# ------------------------------------------------------------------------
asap7_cell_library(
name = "asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args),
srcs = [
":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-libgz".format(**args),
#":asap7-srams-sc{tracks}_rev{rev}-libgz".format(**args),
":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lib7z".format(**args),
#":asap7-srams-sc{tracks}_rev{rev}-lib7z".format(**args),
],
cell_lef = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lef".format(**args),
platform_gds = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-gds".format(**args),
Expand All @@ -137,42 +153,24 @@ def asap7_cells_files(name=None, rev=None, tracks=None, vt=None, has_gds=True):
tech_lef = ":asap7-misc-sc{tracks}_rev{rev}-lef".format(**args),
visibility = [
"//visibility:public",
]
],
)


def _asap7_cell_library_impl(ctx):
liberty_files = [file for file in ctx.files.srcs if file.extension == "gz"]
liberty_files = [file for file in liberty_files if "_{}_".format(ctx.attr.default_corner_delay_model) in file.basename]
liberty_files = [file for file in liberty_files if "SRAM" not in file.basename]

uncompressed_files = []
for file in liberty_files:
uncompressed_file = ctx.actions.declare_file(file.basename[:-len(".gz")])
=======
def _asap7_cell_library_impl(ctx):
liberty_files = [file for file in ctx.files.srcs if file.extension == "7z"]
liberty_files = [file for file in liberty_files if "_{}_".format(ctx.attr.default_corner_delay_model) in file.basename]
liberty_files = [file for file in liberty_files if "SRAM" not in file.basename]
liberty_files = [file for file in liberty_files if ctx.attr.cell_type in file.basename]

uncompressed_files = []
for file in liberty_files:
uncompressed_file = ctx.actions.declare_file(file.basename[:-len(".7z")])
>>>>>>> temp-fix-asap7
ctx.actions.run_shell(
outputs = [
uncompressed_file,
],
inputs = [
file,
],
<<<<<<< HEAD
command = "gunzip --to-stdout {compressed_file} > {uncompressed_file}".format(
compressed_file = file.path,
uncompressed_file = uncompressed_file.path,
),
=======
command = "{tool} x -so -- {compressed_file} > {uncompressed_file}".format(
tool = ctx.executable._uncompress.path,
compressed_file = file.path,
Expand All @@ -181,7 +179,6 @@ def _asap7_cell_library_impl(ctx):
tools = [
ctx.executable._uncompress,
],
>>>>>>> temp-fix-asap7
)

uncompressed_files.append(uncompressed_file)
Expand Down Expand Up @@ -227,30 +224,19 @@ asap7_cell_library = rule(
"tech_lef": attr.label(allow_single_file = True, mandatory = True, doc = "The tech lef file for these standard cells"),
"default_corner_swing": attr.string(mandatory = True, values = ["SS", "FF", "TT"]),
"default_corner_delay_model": attr.string(mandatory = True, values = ["ccs", "ccsn", "ccsa"]),
<<<<<<< HEAD
#TODO(b/212480812): Support multiple VTs in a single design.
"openroad_configuration": attr.label(providers = [OpenRoadPdkInfo]),
"cell_lef": attr.label(allow_single_file = True, mandatory = True, doc = "The lef file for the standard cells"),
"platform_gds": attr.label(allow_single_file = True, mandatory = False, doc = "Platform GDS files"),
=======
"cell_type": attr.string(mandatory = True, values = ["RVT", "LVT", "SLVT"]),
#TODO(b/212480812): Support multiple VTs in a single design.
"openroad_configuration": attr.label(providers = [OpenRoadPdkInfo]),
"cell_lef": attr.label(allow_single_file = True, mandatory = True, doc = "The lef file for the standard cells"),
"platform_gds": attr.label(allow_single_file = True, mandatory = True, doc = "Platform GDS files"),
>>>>>>> temp-fix-asap7
"_combine_liberty": attr.label(
default = Label("@rules_hdl//pdk/liberty:combine_liberty"),
executable = True,
cfg = "exec",
),
<<<<<<< HEAD
=======
"_uncompress": attr.label(
default = Label("@7zip//:7za"),
executable = True,
cfg = "exec",
),
>>>>>>> temp-fix-asap7
},
)
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