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Add a line to synth.tcl to remove Yosys $print cells. #208

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merged 2 commits into from
Oct 31, 2023
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Add a line to synth.tcl to remove Yosys $print cells. #208

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17345be
Add a line to synth.tcl to remove Yosys $print cells.
tcal-x Oct 13, 2023
45752ca
Add comment: why we're deleting $print cells.
tcal-x Oct 16, 2023
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5 changes: 5 additions & 0 deletions synthesis/synth.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -52,6 +52,11 @@ yosys proc -nomux
yosys proc_mux
yosys flatten

# Remove $print cells. These cells represent Verilog $display() tasks.
# Some place and route tools cannot handle these in the output Verilog,
# so remove them here.
yosys delete {*/t:$print}

# Remove internal only aliases for public nets and then give created instances
# useful names. At this stage it is mainly flipflops created by the `proc`
# pass.
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