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Adds ability to use standard cells in user provided RTL #347

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merged 4 commits into from
Aug 23, 2024
Merged

Adds ability to use standard cells in user provided RTL #347

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1c77601
Adds ability to set verilog defines on the synthesize_rtl rule
JoshVarga Aug 23, 2024
e899a3e
Allows liberty cells to be manually instantiated in a netlist
QuantamHD Aug 23, 2024
778ef2d
lint fix
QuantamHD Aug 23, 2024
1411c99
fixes copy and paste typos
QuantamHD Aug 23, 2024
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11 changes: 10 additions & 1 deletion synthesis/build_defs.bzl
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Original file line number Diff line number Diff line change
Expand Up @@ -137,6 +137,11 @@ def _synthesize_design_impl(ctx):
for dont_use_pattern in or_config.do_not_use_cell_list:
dont_use_args += " -dont_use {} ".format(dont_use_pattern)

if ctx.attr.verilog_defines:
for define in ctx.attr.verilog_defines:
args.add(define)

standard_cell_black_box = ctx.actions.declare_file("{}_stdcells_blackbox.v".format(ctx.attr.name))
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script_env_files = {
"ABC_SCRIPT": abc_script,
"ADDITIONAL_LIBERTIES": additional_liberty_files,
Expand All @@ -145,6 +150,7 @@ def _synthesize_design_impl(ctx):
"FLIST": verilog_flist,
"LIBERTY": default_liberty_file,
"OUTPUT": output_file,
"STANDARD_CELL_BLACK_BOX": standard_cell_black_box,
"TOP": ctx.attr.top_module,
"UHDM_FLIST": uhdm_flist,
}
Expand Down Expand Up @@ -178,7 +184,7 @@ def _synthesize_design_impl(ctx):
env[k] = v

ctx.actions.run(
outputs = [output_file, log_file],
outputs = [output_file, log_file, standard_cell_black_box],
inputs = inputs,
arguments = [args],
executable = ctx.executable.yosys_tool,
Expand Down Expand Up @@ -343,6 +349,9 @@ synthesize_rtl = rule(
"top_module": attr.string(
default = "top",
),
"verilog_defines": attr.string_list(
doc = "Verilog defines to pass to the synthesis tool.",
),
"yosys_tool": attr.label(
default = Label("@at_clifford_yosys//:yosys"),
executable = True,
Expand Down
11 changes: 11 additions & 0 deletions synthesis/synth.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -12,11 +12,22 @@

yosys -import

set all_liberties [split $::env(ADDITIONAL_LIBERTIES) ","]
lappend all_liberties $::env(LIBERTY)

# create liberty blackbox so cells can be manually created.
foreach lib $all_liberties {
read_liberty -lib -overwrite $lib
}

write_verilog -blackboxes $::env(STANDARD_CELL_BLACK_BOX)

# read design
set srcs_flist_path $::env(FLIST)
set srcs_flist_file [open $srcs_flist_path "r"]
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set srcs_flist_data [read $srcs_flist_file]
set srcs [split $srcs_flist_data "\n"]
set srcs [linsert $srcs 0 $::env(STANDARD_CELL_BLACK_BOX)]
puts $srcs
foreach src $srcs {
# Skip empty lines, including the implict one after the last \n delimiter
Expand Down
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