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fix VhdlExtractor.is_array + use setup.cfg + clean #10
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1 @@ | ||
__version__ = '1.1.0' |
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Original file line number | Diff line number | Diff line change |
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|
@@ -6,7 +6,8 @@ | |
import os | ||
import re | ||
from pprint import pprint | ||
from hdlparse.minilexer import MiniLexer | ||
from typing import List, Optional | ||
from .minilexer import MiniLexer | ||
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"""VHDL documentation parser""" | ||
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@@ -171,20 +172,48 @@ def __init__(self, name, desc=None): | |
self.kind = 'unknown' | ||
self.desc = desc | ||
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def remove_outer_parenthesis(s: Optional[str]): | ||
if s: | ||
n = 1 | ||
while n: | ||
s, n = re.subn(r'\([^()]*\)', '', s.strip()) # remove non-nested/flat balanced parts | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Couple of things here:
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return s | ||
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class VhdlParameterType: | ||
"""Parameter type definition | ||
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||
Args: | ||
name (str): Name of the type | ||
direction(str): "to" or "downto" | ||
r_bound (str): A simple expression based on digits or variable names | ||
l_bound (str): A simple expression based on digits or variable names | ||
arange (str): Original array range string | ||
""" | ||
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def __init__(self, name, direction="", r_bound="", l_bound="", arange=""): | ||
self.name = name | ||
self.direction = direction.lower().strip() | ||
self.r_bound = r_bound.strip() | ||
self.l_bound = l_bound.strip() | ||
self.arange = arange | ||
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def __repr__(self): | ||
return f"VhdlParameterType('{self.name}','{self.arange}')" | ||
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class VhdlParameter: | ||
"""Parameter to subprograms, ports, and generics | ||
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Args: | ||
name (str): Name of the object | ||
mode (str): Direction mode for the parameter | ||
data_type (str): Type name for the parameter | ||
default_value (str): Default value of the parameter | ||
desc (str): Description from object metacomments | ||
param_desc (str): Description of the parameter | ||
mode (optional str): Direction mode for the parameter | ||
data_type (optional VhdlParameterType): Type name for the parameter | ||
default_value (optional str): Default value of the parameter | ||
desc (optional str): Description from object metacomments | ||
param_desc (optional str): Description of the parameter | ||
""" | ||
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def __init__(self, name, mode=None, data_type=None, default_value=None, desc=None, param_desc=None): | ||
def __init__(self, name, mode: Optional[str] = None, data_type: Optional[VhdlParameterType] = None, default_value: Optional[str] = None, desc: Optional[str] = None, param_desc: Optional[str] = None): | ||
self.name = name | ||
self.mode = mode | ||
self.data_type = data_type | ||
|
@@ -210,28 +239,6 @@ def __repr__(self): | |
return f"VhdlParameter('{self.name}', '{self.mode}', '{self.data_type.name + self.data_type.arange}')" | ||
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class VhdlParameterType: | ||
"""Parameter type definition | ||
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Args: | ||
name (str): Name of the type | ||
direction(str): "to" or "downto" | ||
r_bound (str): A simple expression based on digits or variable names | ||
l_bound (str): A simple expression based on digits or variable names | ||
arange (str): Original array range string | ||
""" | ||
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def __init__(self, name, direction="", r_bound="", l_bound="", arange=""): | ||
self.name = name | ||
self.direction = direction.strip() | ||
self.r_bound = r_bound.strip() | ||
self.l_bound = l_bound.strip() | ||
self.arange = arange | ||
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def __repr__(self): | ||
return f"VhdlParameterType('{self.name}','{self.arange}')" | ||
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class VhdlPackage(VhdlObject): | ||
"""Package declaration | ||
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|
@@ -357,7 +364,7 @@ class VhdlEntity(VhdlObject): | |
desc (str, optional): Description from object metacomments | ||
""" | ||
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def __init__(self, name, ports, generics=None, sections=None, desc=None): | ||
def __init__(self, name: str, ports: List[VhdlParameter], generics: List[VhdlParameter] = [], sections: List[str] = [], desc: Optional[str] = None): | ||
VhdlObject.__init__(self, name, desc) | ||
self.kind = 'entity' | ||
self.generics = generics if generics is not None else [] | ||
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@@ -602,7 +609,7 @@ def parse_vhdl(text): | |
saved_type = groups[0] | ||
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elif action in ( | ||
'array_type', 'file_type', 'access_type', 'record_type', 'range_type', 'enum_type', 'incomplete_type'): | ||
'array_type', 'file_type', 'access_type', 'record_type', 'range_type', 'enum_type', 'incomplete_type'): | ||
vobj = VhdlType(saved_type, cur_package, action, metacomments) | ||
objects.append(vobj) | ||
kind = None | ||
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@@ -684,7 +691,7 @@ def is_vhdl(fname): | |
Returns: | ||
True when file has a VHDL extension. | ||
""" | ||
return os.path.splitext(fname)[1].lower() in ('.vhdl', '.vhd') | ||
return os.path.splitext(fname)[-1].lower() in ('.vhdl', '.vhd') | ||
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class VhdlExtractor: | ||
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@@ -721,7 +728,11 @@ def extract_objects(self, fname, type_filter=None): | |
self._register_array_types(objects) | ||
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if type_filter: | ||
objects = [o for o in objects if isinstance(o, type_filter)] | ||
if not isinstance(type_filter, list): | ||
type_filter = [type_filter] | ||
objects = [ | ||
o for o in objects if any(map(lambda clz: isinstance(o, clz), type_filter)) | ||
] | ||
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return objects | ||
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@@ -750,11 +761,7 @@ def is_array(self, data_type): | |
Returns: | ||
True if ``data_type`` is a known array type. | ||
""" | ||
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# Split off any brackets | ||
data_type = data_type.split('[')[0].strip() | ||
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return data_type.lower() in self.array_types | ||
return data_type.name.lower() in self.array_types | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Passing in |
||
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def _add_array_types(self, type_defs): | ||
"""Add array data types to internal registry | ||
|
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,31 @@ | ||
[metadata] | ||
name = hdlparse | ||
author = Kevin Thibedeau | ||
author_email = [email protected] | ||
url = http://kevinpt.github.io/hdlparse | ||
download_url = http://kevinpt.github.io/hdlparse | ||
description = HDL parser | ||
long_description = file: README.rst | ||
description_file = README.rst | ||
version = attr: hdlparse.__version__ | ||
license = MIT | ||
keywords = HDL parser | ||
classifiers = | ||
Development Status :: 5 - Production/Stable | ||
Operating System :: OS Independent | ||
Intended Audience :: Developers | ||
Topic :: Text Processing :: General | ||
Natural Language :: English | ||
Programming Language :: Python :: 3 | ||
License :: OSI Approved :: MIT License | ||
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[options] | ||
packages = hdlparse | ||
py_modules = | ||
install_requires = | ||
include_package_data = True | ||
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[pycodestyle] | ||
max_line_length = 120 | ||
ignore = E501 |
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---|---|---|
@@ -1,44 +1,3 @@ | ||
from setuptools import setup | ||
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# Use README.rst for the long description | ||
with open('README.rst') as fh: | ||
long_description = fh.read() | ||
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# Scan the script for the version string | ||
version_file = 'hdlparse/minilexer.py' | ||
version = None | ||
with open(version_file) as fh: | ||
try: | ||
version = [line.split('=')[1].strip().strip("'") for line in fh if | ||
line.startswith('__version__')][0] | ||
except IndexError: | ||
pass | ||
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if version is None: | ||
raise RuntimeError('Unable to find version string in file: {0}'.format(version_file)) | ||
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setup(name='hdlparse', | ||
version=version, | ||
author='Kevin Thibedeau', | ||
author_email='[email protected]', | ||
url='http://kevinpt.github.io/hdlparse', | ||
download_url='http://kevinpt.github.io/hdlparse', | ||
description='HDL parser', | ||
long_description=long_description, | ||
platforms=['Any'], | ||
install_requires=[], | ||
packages=['hdlparse'], | ||
py_modules=[], | ||
include_package_data=True, | ||
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keywords='HDL parser', | ||
license='MIT', | ||
classifiers=['Development Status :: 5 - Production/Stable', | ||
'Operating System :: OS Independent', | ||
'Intended Audience :: Developers', | ||
'Topic :: Text Processing :: General', | ||
'Natural Language :: English', | ||
'Programming Language :: Python :: 3', | ||
'License :: OSI Approved :: MIT License' | ||
] | ||
) | ||
setup() |
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The verilog parser currently offers next to no SystemVerilog extension support, so I'm not sure we should add
.sv
here unless we intend to start adding minimal support. The problem is even if all we did was parselogic
, I'm pretty sure something likewire [7:0] logic
is valid verilog... We'd ideally want to make it an optional flag.I am in favor of basic support as I mention here:
#4 (comment)
but we can maybe start a different branch / PR for that?