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fix VhdlExtractor.is_array + use setup.cfg + clean #10
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,2 @@ | ||
"""Parse Verilog and VHDL files""" | ||
__version__ = '1.1.0' |
Original file line number | Diff line number | Diff line change |
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@@ -1,13 +1,12 @@ | ||
# -*- coding: utf-8 -*- | ||
# Copyright © 2017 Kevin Thibedeau | ||
# Distributed under the terms of the MIT license | ||
"""Verilog documentation parser""" | ||
import io | ||
import os | ||
from collections import OrderedDict | ||
from .minilexer import MiniLexer | ||
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from hdlparse.minilexer import MiniLexer | ||
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"""Verilog documentation parser""" | ||
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verilog_tokens = { | ||
# state | ||
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@@ -25,7 +24,7 @@ | |
r'^[\(\s]*(input|inout|output)\s+(reg|supply0|supply1|tri|triand|trior|tri0|tri1|wire|wand|wor)?' | ||
r'\s*(signed)?\s*((\[[^]]+\])+)?', | ||
'module_port_start', 'module_port'), | ||
(r'endmodule', 'end_module', '#pop'), | ||
(r'\bendmodule\b', 'end_module', '#pop'), | ||
(r'/\*', 'block_comment', 'block_comment'), | ||
(r'//#\s*{{(.*)}}\n', 'section_meta'), | ||
(r'//.*\n', None), | ||
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@@ -110,11 +109,12 @@ def parse_verilog_file(fname): | |
"""Parse a named Verilog file | ||
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Args: | ||
fname (str): File to parse. | ||
fname (str): File to parse | ||
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Returns: | ||
List of parsed objects. | ||
List of parsed objects | ||
""" | ||
with open(fname, 'rt') as fh: | ||
with open(fname, 'rt', encoding='UTF-8') as fh: | ||
text = fh.read() | ||
return parse_verilog(text) | ||
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@@ -130,25 +130,21 @@ def parse_verilog(text): | |
lex = VerilogLexer | ||
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name = None | ||
kind = None | ||
saved_type = None | ||
mode = 'input' | ||
port_type = 'wire' | ||
param_type = '' | ||
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metacomments = [] | ||
parameters = [] | ||
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generics = [] | ||
ports = OrderedDict() | ||
sections = [] | ||
port_param_index = 0 | ||
last_item = None | ||
array_range_start_pos = 0 | ||
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objects = [] | ||
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for pos, action, groups in lex.run(text): | ||
for _, action, groups in lex.run(text): | ||
if action == 'metacomment': | ||
comment = groups[0].strip() | ||
if last_item is None: | ||
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@@ -160,7 +156,6 @@ def parse_verilog(text): | |
sections.append((port_param_index, groups[0])) | ||
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elif action == 'module': | ||
kind = 'module' | ||
name = groups[0] | ||
generics = [] | ||
ports = OrderedDict() | ||
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@@ -226,7 +221,7 @@ def is_verilog(fname): | |
Returns: | ||
True when file has a Verilog extension. | ||
""" | ||
return os.path.splitext(fname)[1].lower() in ('.vlog', '.v') | ||
return os.path.splitext(fname)[-1].lower() in ('.vlog', '.v', '.sv') | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. The verilog parser currently offers next to no SystemVerilog extension support, so I'm not sure we should add I am in favor of basic support as I mention here: but we can maybe start a different branch / PR for that? |
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class VerilogExtractor: | ||
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The small edits here will conflict with
umarcor/doc-btd
, but I'm not sure the status of that PR. I'd ideally merge that before doing clean-up here. It seems our intention is to change the name to pyHDLParser since I don't think we can get the PyPI namespace unless we hear back from Kevin.