Merge pull request #1088 from luojia65/main

riscv64: replace deprecated legacy extensions to SBI 2.0 extensions

Cargo.toml

@@ -137,7 +137,7 @@ semihosting = { version = "0.1", optional = true }
 
 [target.'cfg(target_arch = "riscv64")'.dependencies]
 riscv = "0.11"
-sbi = "0.2"
+sbi-rt = "0.0.3"
 trapframe = "0.9"
 semihosting = { version = "0.1", optional = true }
 

src/arch/riscv64/kernel/mod.rs

@@ -123,7 +123,7 @@ pub fn message_output_init() {
 
 pub fn output_message_buf(buf: &[u8]) {
 	for byte in buf {
-		sbi::legacy::console_putchar(*byte);
+		sbi_rt::console_write_byte(*byte);
 	}
 }
 
@@ -198,7 +198,7 @@ fn finish_processor_init() {
 
 		//When running bare-metal/QEMU we use the firmware to start the next hart
 		if !env::is_uhyve() {
-			sbi::hart_state_management::hart_start(
+			sbi_rt::hart_start(
 				next_hart_id as usize,
 				start::_start as usize,
 				RAW_BOOT_INFO.load(Ordering::Relaxed) as usize,

src/arch/riscv64/kernel/processor.rs

@@ -234,7 +234,10 @@ pub fn shutdown(error_code: i32) -> ! {
 			semihosting::process::exit(error_code)
 		} else {
 			// use SBI shutdown
-			sbi::legacy::shutdown()
+			sbi_rt::system_reset(sbi_rt::Shutdown, sbi_rt::NoReason);
+			loop {
+				core::hint::spin_loop();
+			}
 		}
 	}
 }
@@ -270,16 +273,16 @@ pub fn set_oneshot_timer(wakeup_time: Option<u64>) {
 		}
 		let next_time = wt * u64::from(get_frequency());
 
-		sbi::legacy::set_timer(next_time);
+		sbi_rt::set_timer(next_time);
 	} else {
 		// Disable the Timer (and clear a pending interrupt)
 		debug!("Stopping Timer");
-		sbi::legacy::set_timer(u64::MAX);
+		sbi_rt::set_timer(u64::MAX);
 	}
 }
 
 pub fn wakeup_core(core_to_wakeup: CoreId) {
 	let hart_id = unsafe { HARTS_AVAILABLE[core_to_wakeup as usize] };
 	debug!("Wakeup core: {} , hart_id: {}", core_to_wakeup, hart_id);
-	sbi::legacy::send_ipi(&[1 << hart_id]);
+	sbi_rt::send_ipi(sbi_rt::HartMask::from_mask_base(0b1, hart_id));
 }