build(deps): bump x86_64 from 0.14.12 to 0.15.0

Bumps [x86_64](https://github.com/rust-osdev/x86_64) from 0.14.12 to 0.15.0.
- [Changelog](https://github.com/rust-osdev/x86_64/blob/master/Changelog.md)
- [Commits](rust-osdev/x86_64@v0.14.12...v0.15.0)

---
updated-dependencies:
- dependency-name: x86_64
  dependency-type: direct:production
  update-type: version-update:semver-minor
...

Signed-off-by: dependabot[bot] <[email protected]>

Cargo.toml

@@ -126,7 +126,7 @@ features = [
 multiboot = "0.8"
 uart_16550 = "0.3"
 x86 = { version = "0.52", default-features = false }
-x86_64 = "0.14"
+x86_64 = "0.15"
 qemu-exit = "3.0"
 
 [target.'cfg(target_arch = "aarch64")'.dependencies]

src/arch/x86_64/kernel/apic.rs

@@ -477,19 +477,19 @@ pub fn init() {
 	// Set gates to ISRs for the APIC interrupts we are going to enable.
 	unsafe {
 		let mut idt = IDT.lock();
-		idt[ERROR_INTERRUPT_NUMBER as usize]
+		idt[ERROR_INTERRUPT_NUMBER]
 			.set_handler_fn(error_interrupt_handler)
 			.set_stack_index(0);
-		idt[SPURIOUS_INTERRUPT_NUMBER as usize]
+		idt[SPURIOUS_INTERRUPT_NUMBER]
 			.set_handler_fn(spurious_interrupt_handler)
 			.set_stack_index(0);
 		#[cfg(feature = "smp")]
 		{
-			idt[TLB_FLUSH_INTERRUPT_NUMBER as usize]
+			idt[TLB_FLUSH_INTERRUPT_NUMBER]
 				.set_handler_fn(tlb_flush_handler)
 				.set_stack_index(0);
 			interrupts::add_irq_name(TLB_FLUSH_INTERRUPT_NUMBER - 32, "TLB flush");
-			idt[WAKEUP_INTERRUPT_NUMBER as usize]
+			idt[WAKEUP_INTERRUPT_NUMBER]
 				.set_handler_fn(wakeup_handler)
 				.set_stack_index(0);
 			interrupts::add_irq_name(WAKEUP_INTERRUPT_NUMBER - 32, "Wakeup");

src/arch/x86_64/kernel/gdt.rs

@@ -18,14 +18,14 @@ use crate::config::KERNEL_STACK_SIZE;
 
 pub fn add_current_core() {
 	let gdt: &mut GlobalDescriptorTable = Box::leak(Box::new(GlobalDescriptorTable::new()));
-	let kernel_code_selector = gdt.add_entry(Descriptor::kernel_code_segment());
-	let kernel_data_selector = gdt.add_entry(Descriptor::kernel_data_segment());
+	let kernel_code_selector = gdt.append(Descriptor::kernel_code_segment());
+	let kernel_data_selector = gdt.append(Descriptor::kernel_data_segment());
 	#[cfg(feature = "common-os")]
 	{
 		let _user_code32_selector =
-			gdt.add_entry(Descriptor::UserSegment(DescriptorFlags::USER_CODE32.bits()));
-		let _user_data64_selector = gdt.add_entry(Descriptor::user_data_segment());
-		let _user_code64_selector = gdt.add_entry(Descriptor::user_code_segment());
+			gdt.append(Descriptor::UserSegment(DescriptorFlags::USER_CODE32.bits()));
+		let _user_data64_selector = gdt.append(Descriptor::user_data_segment());
+		let _user_code64_selector = gdt.append(Descriptor::user_code_segment());
 	}
 
 	// Dynamically allocate memory for a Task-State Segment (TSS) for this core.
@@ -53,7 +53,7 @@ pub fn add_current_core() {
 	}
 
 	CoreLocal::get().tss.set(tss);
-	let tss_selector = gdt.add_entry(Descriptor::tss_segment(tss));
+	let tss_selector = gdt.append(Descriptor::tss_segment(tss));
 
 	// Load the GDT for the current core.
 	gdt.load();

src/arch/x86_64/kernel/interrupts.rs

@@ -40,7 +40,7 @@ pub(crate) fn install() {
 	set_general_handler!(&mut *idt, unknown, 64..);
 
 	unsafe {
-		for i in 32..256 {
+		for i in 32..=255 {
 			let addr = idt[i].handler_addr();
 			idt[i].set_handler_addr(addr).set_stack_index(0);
 		}
@@ -117,7 +117,7 @@ pub extern "C" fn irq_install_handler(
 
 	let mut idt = IDT.lock();
 	unsafe {
-		idt[(32 + irq_number) as usize]
+		idt[32 + irq_number]
 			.set_handler_addr(x86_64::VirtAddr::new(
 				u64::try_from(handler as usize).unwrap(),
 			))

src/arch/x86_64/kernel/pic.rs

@@ -34,10 +34,10 @@ pub fn init() {
 	// This is especially true for real hardware. So provide a handler for them.
 	unsafe {
 		let mut idt = IDT.lock();
-		idt[(PIC1_INTERRUPT_OFFSET + SPURIOUS_IRQ_NUMBER) as usize]
+		idt[PIC1_INTERRUPT_OFFSET + SPURIOUS_IRQ_NUMBER]
 			.set_handler_fn(spurious_interrupt_on_master)
 			.set_stack_index(0);
-		idt[(PIC2_INTERRUPT_OFFSET + SPURIOUS_IRQ_NUMBER) as usize]
+		idt[PIC2_INTERRUPT_OFFSET + SPURIOUS_IRQ_NUMBER]
 			.set_handler_fn(spurious_interrupt_on_slave)
 			.set_stack_index(0);
 

src/arch/x86_64/kernel/processor.rs

@@ -416,7 +416,7 @@ impl CpuFrequency {
 		// system timer with a known constant frequency.
 		unsafe {
 			let mut idt = IDT.lock();
-			idt[pit::PIT_INTERRUPT_NUMBER as usize]
+			idt[pit::PIT_INTERRUPT_NUMBER]
 				.set_handler_fn(Self::measure_frequency_timer_handler)
 				.set_stack_index(0);
 		}

src/arch/x86_64/kernel/scheduler.rs

@@ -388,7 +388,7 @@ extern "x86-interrupt" fn timer_handler(_stack_frame: interrupts::ExceptionStack
 pub fn install_timer_handler() {
 	unsafe {
 		let mut idt = IDT.lock();
-		idt[apic::TIMER_INTERRUPT_NUMBER as usize]
+		idt[apic::TIMER_INTERRUPT_NUMBER]
 			.set_handler_fn(timer_handler)
 			.set_stack_index(0);
 	}

src/arch/x86_64/kernel/serial.rs

@@ -92,7 +92,7 @@ extern "x86-interrupt" fn serial_interrupt(_stack_frame: crate::interrupts::Exce
 pub(crate) fn install_serial_interrupt() {
 	unsafe {
 		let mut idt = IDT.lock();
-		idt[SERIAL_IRQ.into()]
+		idt[SERIAL_IRQ]
 			.set_handler_fn(serial_interrupt)
 			.set_stack_index(0);
 	}

src/arch/x86_64/mm/paging.rs

@@ -268,7 +268,7 @@ pub(crate) extern "x86-interrupt" fn page_fault_handler(
 	error_code: PageFaultErrorCode,
 ) {
 	error!("Page fault (#PF)!");
-	error!("page_fault_linear_address = {:p}", Cr2::read());
+	error!("page_fault_linear_address = {:p}", Cr2::read().unwrap());
 	error!("error_code = {error_code:?}");
 	error!("fs = {:#X}", processor::readfs());
 	error!("gs = {:#X}", processor::readgs());
@@ -397,7 +397,7 @@ pub(crate) unsafe fn print_page_tables(levels: usize) {
 	}
 
 	// Recursive
-	let mut recursive_page_table = unsafe { recursive_page_table() };
+	let recursive_page_table = unsafe { recursive_page_table() };
 	let pt = recursive_page_table.level_4_table();
 
 	// Identity mapped