Merge pull request #1087 from stlankes/toolchain

switch to the nightly compiler from 1st of March

rust-toolchain.toml

@@ -1,5 +1,5 @@
 [toolchain]
-channel = "nightly-2024-02-15"
+channel = "nightly-2024-03-01"
 components = [
     "llvm-tools",
     "rust-src",

src/arch/x86_64/kernel/processor.rs

@@ -944,7 +944,7 @@ pub fn seed_entropy() -> Option<[u8; 32]> {
 			// flag was incorrectly set without there actually being a random value
 			// available. Even though no bugs are known for RDSEED, we should not
 			// consider the default values random for extra security.
-			while unsafe { _rdseed64_step(&mut value) != 1 } || value == 0 || value == !0 {
+			while unsafe { _rdseed64_step(&mut value) != 1 } || value == 0 || value == u64::MAX {
 				// Spin as per the recommendation in the
 				// Intel® Digital Random Number Generator (DRNG) implementation guide
 				spin_loop();

src/arch/x86_64/mm/paging.rs

@@ -182,7 +182,7 @@ pub fn map<S>(
 
 /// Maps `count` pages at address `virt_addr`. If the allocation of a physical memory failed,
 /// the number of successfull mapped pages are returned as error value.
-pub fn map_heap<S: PageSize>(virt_addr: VirtAddr, count: usize) -> Result<(), usize>
+pub fn map_heap<S>(virt_addr: VirtAddr, count: usize) -> Result<(), usize>
 where
 	S: PageSize + Debug,
 	RecursivePageTable<'static>: Mapper<S>,

src/drivers/net/virtio_net.rs

@@ -8,7 +8,6 @@ use alloc::vec::Vec;
 use core::cell::RefCell;
 use core::cmp::Ordering;
 use core::mem;
-use core::result::Result;
 
 use align_address::Align;
 use pci_types::InterruptLine;

src/drivers/virtio/env.rs

@@ -179,7 +179,6 @@ pub mod memory {
 #[cfg(feature = "pci")]
 pub mod pci {
 	use alloc::vec::Vec;
-	use core::result::Result;
 
 	use pci_types::{Bar, MAX_BARS};
 

src/drivers/virtio/transport/mmio.rs

@@ -3,9 +3,7 @@
 //! The module contains ...
 #![allow(dead_code)]
 
-use core::convert::TryInto;
 use core::ptr::{read_volatile, write_volatile};
-use core::result::Result;
 use core::sync::atomic::{fence, Ordering};
 use core::{ptr, u8};
 

src/drivers/virtio/transport/pci.rs

@@ -4,7 +4,6 @@
 #![allow(dead_code)]
 
 use alloc::vec::Vec;
-use core::result::Result;
 use core::sync::atomic::{fence, Ordering};
 use core::{mem, ptr};
 

src/scheduler/mod.rs

@@ -16,7 +16,7 @@ use core::task::Poll::Ready;
 use ahash::RandomState;
 use crossbeam_utils::Backoff;
 use hashbrown::HashMap;
-use hermit_sync::{without_interrupts, *};
+use hermit_sync::*;
 #[cfg(target_arch = "riscv64")]
 use riscv::register::sstatus;