All the patterns & designs are given above, but sram files are not given, including:
- testbed.v
- pattern.v
- design.v
- syn.tcl
- chip_shell.v
- chip.io
- chip.sdc
course outline
- lab1 → combinational circuit
- lab2 → sequential circuit
- lab3 → testbench & pattern
- lab4 → IP
- lab5 → SRAM
- lab6 → synthesis, design compiler
- lab7 → STA, CDC, cross clk domain
- lab8 → low power
- lab9 → SystemVerilog design
- lab10 → SystemVerilog verification
- lab11 → APR1
- lab12 → APR2, with IR drop
- bonus → formal verification
pdf file password: 秋天年分這堂課的英文小寫
If anything bother, please contact: [email protected]
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