Digital-lock-with-VHDL

Coding platform: Vivado2017

Development board: Nexys4 DDR FPGA Board

Functions:

including 6 states(original state, user state, admin state, unlock state, alarm state, error state)
The user enters the password no more than 3 times and it turns into alarm state otherwise.
The admin changes the password or shuts the alarm in admin state.
The system goes back to the original state with no inkeys more than 10 sec (20 sec when unlock and admin state).

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
README.md		README.md
deshake.vhd		deshake.vhd
divclk.vhd		divclk.vhd
divclk_2.vhd		divclk_2.vhd
e_lock.vhd		e_lock.vhd
lock_ts.vhd		lock_ts.vhd

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