Merge pull request #1 from alibillalhammoud/main

Adding more LLM code from Ali's repository

openfasoc/generators/glayout/glayout/flow/routing/smart_route.py

@@ -264,48 +264,54 @@ def generic_route_ab_ba_common_centroid(
     # TODO: implement
     name1, name2 = parse_port_name(edge1.name), parse_port_name(edge2.name)
     width1 = edge1.width
+    # grab basename for reading ports
+    basename = edge1.name.rstrip("NESW").rstrip("_")
+    basename = basename.removesuffix("source").removesuffix("drain").removesuffix("gate").rstrip("_")
+    basename = basename.removesuffix("A").removesuffix("B")
+    def get_top_port(prtname):
+        return top_comp.ports[basename + prtname]
     # order names so that A is first (if only one A)
     if "A" in name2 and not("A" in name1):
         name1, name2 = name2, name1
     # same device routes (A->A or B->B) (6/15)
     if check_route(name1,name2,"A_source","A_gate"):
-        return straight_route(pdk, top_comp.ports["A_source_E_private"],top_comp.ports["A_gate_route_con_N"],via2_alignment=("right","bottom"))
+        return straight_route(pdk, get_top_port("A_source_E_private"),get_top_port("A_gate_route_con_N"),via2_alignment=("right","bottom"))
     if check_route(name1,name2,"A_drain","A_gate"):
-        return straight_route(pdk, top_comp.ports["A_drain_E_private"],top_comp.ports["A_gate_route_con_N"],via2_alignment=("right","top"))
+        return straight_route(pdk, get_top_port("A_drain_E_private"),get_top_port("A_gate_route_con_N"),via2_alignment=("right","top"))
     if check_route(name1,name2,"A_source","A_drain"):
-        straight_route(pdk, top_comp.ports["br_multiplier_0_source_N"],top_comp.ports["br_multiplier_0_drain_S"],width=min(width1,1))
-        return straight_route(pdk, top_comp.ports["tl_multiplier_0_source_S"],top_comp.ports["tl_multiplier_0_drain_N"],width=min(width1,1))
+        straight_route(pdk, get_top_port("br_multiplier_0_source_N"),get_top_port("br_multiplier_0_drain_S"),width=min(width1,1))
+        return straight_route(pdk, get_top_port("tl_multiplier_0_source_S"),get_top_port("tl_multiplier_0_drain_N"),width=min(width1,1))
     if check_route(name1,name2,"B_source","B_gate"):
-        return straight_route(pdk, top_comp.ports["B_source_W_private"],top_comp.ports["B_gate_route_con_N"],via2_alignment=("left","bottom"))
+        return straight_route(pdk, get_top_port("B_source_W_private"),get_top_port("B_gate_route_con_N"),via2_alignment=("left","bottom"))
     if check_route(name1,name2,"B_drain","B_gate"):
-        return straight_route(pdk, top_comp.ports["B_drain_W_private"],top_comp.ports["B_gate_route_con_N"],via2_alignment=("left","top"))
+        return straight_route(pdk, get_top_port("B_drain_W_private"),get_top_port("B_gate_route_con_N"),via2_alignment=("left","top"))
     if check_route(name1,name2,"B_source","B_drain"):
-        top_comp << straight_route(pdk, top_comp.ports["tr_multiplier_0_source_S"],top_comp.ports["tr_multiplier_0_drain_N"],width=min(width1,1))
-        return straight_route(pdk, top_comp.ports["bl_multiplier_0_source_N"],top_comp.ports["bl_multiplier_0_drain_S"],width=min(width1,1))
+        top_comp << straight_route(pdk, get_top_port("tr_multiplier_0_source_S"),get_top_port("tr_multiplier_0_drain_N"),width=min(width1,1))
+        return straight_route(pdk, get_top_port("bl_multiplier_0_source_N"),get_top_port("bl_multiplier_0_drain_S"),width=min(width1,1))
     # A_src/drain->B_gate or B_src/drain->A_gate (4/15)
     if check_route(name1,name2,"A_source","B_gate"):
-        return straight_route(pdk, top_comp.ports["A_source_W_private"],top_comp.ports["B_gate_route_con_N"],via2_alignment=("left","top"))
+        return straight_route(pdk, get_top_port("A_source_W_private"),get_top_port("B_gate_route_con_N"),via2_alignment=("left","top"))
     if check_route(name1,name2,"A_drain","B_gate"):
-        return straight_route(pdk, top_comp.ports["A_drain_W_private"],top_comp.ports["B_gate_route_con_N"],via2_alignment=("left","bottom"))
+        return straight_route(pdk, get_top_port("A_drain_W_private"),get_top_port("B_gate_route_con_N"),via2_alignment=("left","bottom"))
     if check_route(name1,name2,"B_source","A_gate"):
-        return straight_route(pdk, top_comp.ports["B_source_E_private"],top_comp.ports["A_gate_route_con_N"],via2_alignment=("right","top"))
+        return straight_route(pdk, get_top_port("B_source_E_private"),get_top_port("A_gate_route_con_N"),via2_alignment=("right","top"))
     if check_route(name1,name2,"B_drain","A_gate"):
-        return straight_route(pdk, top_comp.ports["B_drain_E_private"],top_comp.ports["A_gate_route_con_N"],via2_alignment=("right","bottom"))
+        return straight_route(pdk, get_top_port("B_drain_E_private"),get_top_port("A_gate_route_con_N"),via2_alignment=("right","bottom"))
     # A_src/drain->B_src or A_src/drain->B_drain (4/15)
     if check_route(name1,name2,"A_source","B_source"):
-        return straight_route(pdk, top_comp.ports["tl_multiplier_0_source_E"],top_comp.ports["tr_multiplier_0_source_W"])
+        return straight_route(pdk, get_top_port("tl_multiplier_0_source_E"),get_top_port("tr_multiplier_0_source_W"))
     if check_route(name1,name2,"A_drain","B_source"):
-        portmv1 = top_comp.ports["tl_multiplier_0_drain_E"].copy()
-        return straight_route(pdk, top_comp.ports["tl_multiplier_0_drain_E"],movex(portmv1,2*pdk.get_grule(pdk.layer_to_glayer(portmv1.layer))["min_separation"]))
+        portmv1 = get_top_port("tl_multiplier_0_drain_E").copy()
+        return straight_route(pdk, get_top_port("tl_multiplier_0_drain_E"),movex(portmv1,2*pdk.get_grule(pdk.layer_to_glayer(portmv1.layer))["min_separation"]))
     if check_route(name1,name2,"A_source","B_drain"):
-        portmv1 = top_comp.ports["tr_multiplier_0_drain_W"].copy()
-        return straight_route(pdk, top_comp.ports["tr_multiplier_0_drain_W"],movex(portmv1,-2*pdk.get_grule(pdk.layer_to_glayer(portmv1.layer))["min_separation"]))
+        portmv1 = get_top_port("tr_multiplier_0_drain_W").copy()
+        return straight_route(pdk, get_top_port("tr_multiplier_0_drain_W"),movex(portmv1,-2*pdk.get_grule(pdk.layer_to_glayer(portmv1.layer))["min_separation"]))
     if check_route(name1,name2,"A_drain","B_drain"):
-        portmv1 = top_comp.ports["bl_mutliplier_0_drain_N"].copy()
-        portmv2 = top_comp.ports["br_multiplier_0_drain_N"].copy()
-        top_comp << straight_route(pdk, movex(portmv1,-portmv1.width/2), top_comp.ports["tl_multiplier_0_drain_S"],width=width1)
-        return straight_route(pdk, movex(portmv2,portmv2.width/2),top_comp.ports["tr_multiplier_0_drain_S"])
+        portmv1 = get_top_port("bl_mutliplier_0_drain_N").copy()
+        portmv2 = get_top_port("br_multiplier_0_drain_N").copy()
+        top_comp << straight_route(pdk, movex(portmv1,-portmv1.width/2), get_top_port("tl_multiplier_0_drain_S"),width=width1)
+        return straight_route(pdk, movex(portmv2,portmv2.width/2),get_top_port("tr_multiplier_0_drain_S"))
     # A_gate -> B_gate (1/15)
     if check_route(name1,name2,"A_gate","B_gate"):
-        return straight_route(pdk,top_comp.ports["br_multiplier_0_gate_W"],top_comp.ports["bl_multiplier_0_gate_E"])
+        return straight_route(pdk,get_top_port("br_multiplier_0_gate_W"),get_top_port("bl_multiplier_0_gate_E"))
     raise ValueError("You picked a port that smart_route with ab_ba_common_centroid does not support")

openfasoc/generators/glayout/glayout/llm/manage_data.py

@@ -217,9 +217,9 @@ def get_prompt_from_template(
     inst_prompt += f"Below is some context on Glayout strictsyntax:\n{glayout_nlp_context}\n\n"
     #inst_prompt += "Below is context on the circuit"
     #inst_prompt += "convert an example prompt to Glayout strictsyntax\n"
-    #inst_prompt += f"{ragcontext}\n\n----\nTRANSLATION TASK\n"
+    inst_prompt += f"\n{ragcontext}\n"
     #inst_prompt += f"Do NOT include the context in your response. Convert the following prompt to Glayout strictsyntax:\n{prompt}"
-    inst_prompt += f"Glayout strictsyntax is a electronic circuit layout command language. Convert the following prompt to Glayout strictsyntax:\n{prompt}"
+    inst_prompt += f"Convert the following prompt to Glayout strictsyntax:\n{prompt}"
     # unify prompt and return
     messages = [{"role": "user", "content": inst_prompt}]
     # conditionally add label (expected strict syntax output)
@@ -268,12 +268,14 @@ def load_preprocessed_data_in_messages_format():
     # train
     train_messages = list()
     for prompt, result in train_examples:
-        train_messages.append(get_prompt_from_template(None,None,prompt,result,True))
+        ragcontext = RAGvecdb.query(prompt, 1)
+        train_messages.append(get_prompt_from_template(None,ragcontext,prompt,result,True))
     train_data = Dataset.from_dict({"messages":train_messages})
     # eval
     eval_messages = list()
     for prompt, result in eval_examples:
-        eval_messages.append(get_prompt_from_template(None,None,prompt,result,True))
+        ragcontext = RAGvecdb.query(prompt, 1)
+        eval_messages.append(get_prompt_from_template(None,ragcontext,prompt,result,True))
     eval_data = Dataset.from_dict({"messages":eval_messages})
     return {"train": train_data, "evaluation": eval_data}
 

openfasoc/generators/glayout/glayout/llm/rag_data/CommonSource.md

@@ -1,15 +1,2 @@
-# Common Source Amplifier 
-The common source amplifier, serves as an amplifier with voltage gain and phase inversion.
-The main amplifying transistor is in a common-source configuration. Its source is connected to a common reference (often ground), its gate receives the input signal, and the drain is connected to the active load.
+# Common Source Amplifier
 There are two MOSFETs. One acts as the amplifying stage and we will call this M1, and the other is the active load which we will call M2. Depending on the type of active load, the port of the active load corresponding to the direction of current is connected to the drain of M1. The source of M1 is connected to a lower voltage level than the supply.
-Pseudo Netlist:
-an nmos is has the following subckt definition:
-NMOS drain gate source body
-a pmos is has the following subckt definition:
-PMOS drain gate source body
-
-a common source amplifier with a biased pfet transistor has the following subckt definition:
-.subckt commonsourceamp vin vbias vdd vss vout
-m1 vout vin vss vss NMOS
-m2 vout vbias vdd vdd PMOS
-.endsubckt

openfasoc/generators/glayout/glayout/llm/rag_data/CurrentMirror.md

@@ -1,12 +1,4 @@
 # Current Mirror
 A current mirror is a circuit designed to copy a current
 The ratio is the width ratio between mirror and reference, used to tune the relative current between mirror transistor drain and reference transistor drain.
-two transistors (either nfet or pfet) one labeled as the reference which accepts an input current at the drain, and one labeled as mirror which has the output current at the drain. The sources of reference and mirror are connected and the gates of reference and mirror are also connected. The drain of the reference is connected to gate of reference.
-Pseudo Netlist:
-an nmos is has the following subckt definition:
-NMOS drain gate source body
-the nfet current mirror has the following subckt definition:
-.subckt currentmirror inputcurrent outputcurrent
-reference inputcurrent inputcurrent gnd gnd NMOS
-mirror outputcurrent inputcurrent gnd gnd NMOS
-.endsubckt
+two transistors (either nfet or pfet) one labeled as the reference which accepts an input current at the drain, and one labeled as mirror which has the output current at the drain. The sources of reference and mirror are connected and the gates of reference and mirror are also connected. The drain of the reference is connected to gate of reference.

openfasoc/generators/glayout/glayout/llm/rag_data/DeltaSigmaModulator.md

@@ -0,0 +1,2 @@
+# Delta Sigma Modulator ADC
+A delta sigma modulator is a circuit consisting of several existing components including an opamp and a latched comparator. The latched compartor includes a d flip flop and a strong arm latch. All these components can be directly imported. The outputs of the opamp should be connected to the inputs of the latched comparator.

openfasoc/generators/glayout/glayout/llm/rag_data/StrongArmLatch.md

@@ -1,3 +1,2 @@
 # Strong Arm Latch
-A strong arm latch is a comparator (which means it compares two input voltages). If one voltage is higher it outputs a high voltage and if one of them is lower then it output a low voltage.
-A strong arm latch consists of a diffpair. The inputs of the diffpair are the inputs of the strong arm latch. The diff pair outputs are connected to a cross coupled inverter..... drain. There are 2 pfets for... 
+A strong arm latch consists of a diffpair, a CrossCoupleInverters, a bridge nfet, a clkgnd nfet, and two pfets clkpwrL (west) and clkpwrR (east). The cross coupled inverters should be at the top. The bridge should be above the diffpair but below the cross coupled inverters. The clkgnd should be at the bottom, and both clkpwr transistors should be left and right of the cross coupled inverters. You must route the drain of transistor A of the diffpair with the drain of the bridge, the drain of transistor B of the diffpair with the source of the bridge, the source of transistor A in the diffpair with the source of clkgnd.

openfasoc/generators/glayout/glayout/llm/rag_data/diffpair.md

@@ -8,9 +8,6 @@ width: a float parameter specifying the width of all transistor Components part
 fingers: an integer parameter which modifies the number of fingers in all transistor Components which are part of the diff pair.
 ## Ports
 The following are just some examples of the valid ports for diff_pair:
-ComponentRef_A_source_S
-ComponentRef_A_drain_N
-ComponentRef_B_source_S
-ComponentRef_A_gate_E
+ComponentRef_A_source_E
 ComponentRef_B_drain_W
-ComponentRef_B_gate_E
+ComponentRef_A_gate_E

openfasoc/generators/glayout/glayout/llm/rag_data/opamp.md

@@ -1,13 +1,2 @@
 # Opamp
-An operational amplifier or opamp is a voltage amplifying device.
-## Terms Defined
-Inverting Input (IN-): The input terminal where the signal is inversely amplified. <br />
-Non-inverting Input (IN+): The input terminal where the signal is amplified retaining its original phase. <br />
-Output Terminal: Where the amplified signal is provided. <br />
-Power Supply Ports: Two ports, one for the positive power supply voltage (V+), and one for the negative (V-). <br />
-Bias Current: The current that flows into the input terminals due to internal transistor biasing. <br />
-Open-Loop Gain: The amplification factor of the operational amplifier without any feedback. <br />
-Slew Rate: The maximum rate at which the output voltage can change, often specified in V/µs. <br />
-Offset Voltage: A small voltage that must be applied between the input terminals to ensure a zero volt output without any signal.
-### In Words
-The op amp symbol consists of a triangle pointing to the right with five terminals: two input terminals on the left side, one output terminal on the triangle's right tip, and two power supply terminals (-V and +V) at the top and bottom respectively. The non-inverting input (IN+) is usually shown at the top left of the triangle, and the inverting input (IN-) is depicted below it.
+An operational amplifier or opamp is a voltage amplifying device. A 4 stage opamp consists of several integrator stages. 

openfasoc/generators/glayout/glayout/llm/rag_data/pushpullamp.md

@@ -1,23 +1,2 @@
 # Push Pull Amp (Class B Amplifier)
-A push-pull amplifier is a type of amplifier which is able to 
-
-## Terms Defined
-
-Class: The amplifier class, such as Class A, B, AB, or C, indicating the portion of the input signal cycle during which each transistor conducts.
-Active Device: The amplifying element, often a transistor, that can control a large current flow with a smaller input signal.
-Biasing: The process of setting the initial operating point of an active device.
-Crossover Distortion: A form of distortion that occurs in Class B and AB push-pull amplifiers due to the transition between the "push" and "pull" transistors.
-
-## Schematic
-
-### In Words
-
-A push-pull amplifier typically consists of two transistors, an NPN (or N-channel MOSFET) and a PNP (or P-channel MOSFET) transistor. The emitters (or sources) of the two transistors are connected together and to the output load. The bases (or gates) receive the input signal through a phase splitter, which creates two signals that are 180 degrees out of phase with each other. The collectors (or drains) of each transistor are connected to the supply voltages.
-
-### Pseudo Netlist
-
-A push pull amp has the following subckt definition: .subckt pushpullamp input output vcc vee
-Q1 NPN_collector input common vcc NPN
-Q2 PNP_collector input common vee PNP
-.endsubckt
-
+A push-pull amplifier typically consists of two transistors, a nmos and pmos. The sources of the two transistors are connected together and to the output load. The drains of each transistor are connected to the supply voltages.