Final modification of the intergititized layout of the transmission g…

…ate PCell

openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/comp_dc.py

@@ -1,4 +1,5 @@
 def initialise(): 
-    global inv_channel_width_base, tg_channel_width_base 
-    inv_channel_width_base = 3.0
-    tg_channel_width_base = 3.0
+    global inv_fet_width_base, tg_fet_width_base, tg_fet_width_factor
+    inv_fet_width_base = 3.0
+    tg_fet_width_base = 3.0
+    tg_fet_width_factor = tg_fet_width_base*4

openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py

@@ -8,10 +8,12 @@
 TARGET_PDK = sky130
 PWD_OUTPUT = subprocess.run(['pwd'], capture_output=True, text=True)
 GDS_DIR = PWD_OUTPUT.stdout.strip() + "/gds"
+DRC_RPT_DIR = PWD_OUTPUT.stdout.strip() + "/regression/drc"
+LVS_RPT_DIR = PWD_OUTPUT.stdout.strip() + "/regression/lvs"
 
-pmos_width  = 6.0*2
+pmos_width  = 12.0*1
 pmos_length = 0.15
-nmos_width  = 6.0*2
+nmos_width  = 12.0*1
 nmos_length = 0.15
 
 def basic_tg_eval():
@@ -27,15 +29,19 @@ def basic_tg_eval():
 
 	tg_dut.show()
 	tg_dut.write_gds(f"{GDS_DIR}/{tg_dut.name}.gds")
-	'''
 	magic_drc_result = sky130.drc_magic(
 		layout=tg_dut,
-		design_name=tg_dut.name#,
-		#output_file=f"{absolute_path}/{tg.name}.rpt"
+		design_name=tg_dut.name,
+		output_file=f"{DRC_RPT_DIR}/{tg_dut.name}_drc.rpt"
 	)
 	print(f"Magic DRC result ({tg_dut.name}): \n", magic_drc_result)
 	print("--------------------------------------")
-	'''
+	netgen_lvs_result = sky130.lvs_netgen(
+		layout=tg_dut,
+		design_name=tg_dut.name,
+		output_file_path=f"{LVS_RPT_DIR}/{tg_dut.name}_lvs.rpt",
+		copy_intermediate_files=True
+	)
 
 def gate_ctrl_inv_eval():
 	gate_ctrl_inv = reconfig_inv.reconfig_inv(

openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py

@@ -176,7 +176,7 @@ def reconfig_inv(
 ) -> Component:
 	if pmos_width != nmos_width:
 		raise ValueError("PCell constraint: the widths of PMOS and NMOS must be identical")
-	elif pmos_width >= comp_dc.inv_channel_width_base: # Long-channel PMOS and NMOS
+	elif pmos_width >= comp_dc.inv_fet_width_base: # Long-channel PMOS and NMOS
 		inv = long_channel_inv(
 			pdk=pdk,
 			component_name=component_name,

openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/regression/drc/long_width_tg_3f598baa_drc.rpt

@@ -0,0 +1,3 @@
+long_width_tg_3f598baa count: 
+----------------------------------------
+

openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/regression/lvs/long_width_tg_3f598baa_lvs.rpt

@@ -0,0 +1,67 @@
+
+Circuit 1 cell sky130_fd_pr__pfet_01v8 and Circuit 2 cell sky130_fd_pr__pfet_01v8 are black boxes.
+Warning: Equate pins:  cell sky130_fd_pr__pfet_01v8 is a placeholder, treated as a black box.
+Warning: Equate pins:  cell sky130_fd_pr__pfet_01v8 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__pfet_01v8         |Circuit 2: sky130_fd_pr__pfet_01v8         
+-------------------------------------------|-------------------------------------------
+1                                          |1                                          
+2                                          |2                                          
+3                                          |3                                          
+4                                          |4                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__pfet_01v8 and sky130_fd_pr__pfet_01v8 are equivalent.
+
+Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
+Warning: Equate pins:  cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
+Warning: Equate pins:  cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__nfet_01v8         |Circuit 2: sky130_fd_pr__nfet_01v8         
+-------------------------------------------|-------------------------------------------
+1                                          |1                                          
+2                                          |2                                          
+3                                          |3                                          
+4                                          |4                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.
+Flattening unmatched subcell PMOS in circuit long_width_tg_3f598baa (1)(2 instances)
+Flattening unmatched subcell NMOS in circuit long_width_tg_3f598baa (1)(2 instances)
+
+Cell long_width_tg_3f598baa (1) disconnected node: VDD
+Cell long_width_tg_3f598baa (1) disconnected node: VSS
+Class long_width_tg_3f598baa (0):  Merged 6 parallel devices.
+Class long_width_tg_3f598baa (1):  Merged 2 parallel devices.
+Cell long_width_tg_3f598baa (1) disconnected node: VDD
+Cell long_width_tg_3f598baa (1) disconnected node: VSS
+Subcircuit summary:
+Circuit 1: long_width_tg_3f598baa          |Circuit 2: long_width_tg_3f598baa          
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8 (4->1)             |sky130_fd_pr__pfet_01v8 (8->1)             
+sky130_fd_pr__nfet_01v8 (4->1)             |sky130_fd_pr__nfet_01v8 (8->1)             
+Number of devices: 2                       |Number of devices: 2                       
+Number of nets: 6 **Mismatch**             |Number of nets: 5 **Mismatch**             
+---------------------------------------------------------------------------------------
+NET mismatches: Class fragments follow (with fanout counts):
+Circuit 1: long_width_tg_3f598baa          |Circuit 2: long_width_tg_3f598baa          
+
+---------------------------------------------------------------------------------------
+Net: w_n697_603#                           |Net: B                                     
+  sky130_fd_pr__pfet_01v8/4 = 1            |  sky130_fd_pr__pfet_01v8/4 = 1            
+                                           |  sky130_fd_pr__nfet_01v8/4 = 1            
+                                           |                                           
+Net: (no pins)                             |(no matching net)                          
+  sky130_fd_pr__nfet_01v8/4 = 1            |                                           
+---------------------------------------------------------------------------------------
+Netlists do not match.
+
+Subcircuit pins:
+Circuit 1: long_width_tg_3f598baa          |Circuit 2: long_width_tg_3f598baa          
+-------------------------------------------|-------------------------------------------
+Cell pin lists are equivalent.
+Device classes long_width_tg_3f598baa and long_width_tg_3f598baa are equivalent.
+
+Final result: Netlists do not match.