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Fixed LDO Flow #288

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merged 24 commits into from
Aug 22, 2024
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3a7b9c5
fix: use double height site for ldo comparator latch
harshkhandeparkar Jan 5, 2024
683f08b
feat: added unithvdbl site to PLACE_SITE
harshkhandeparkar Jan 5, 2024
7a2770e
fix: updated comparator latch x coordinate to compensate MY orientation
harshkhandeparkar Jan 5, 2024
1e57e5c
fix: updated save_images.tcl
harshkhandeparkar Jan 5, 2024
81c314e
fix: removed commented pmos_2 from domain_insts.txt
harshkhandeparkar Jan 6, 2024
91a2087
fix: increased VREG domain area
harshkhandeparkar Jan 6, 2024
031cdc3
fix: removed pmos_2 from ldo_custom_net.txt
harshkhandeparkar Jan 6, 2024
c3d8867
fix: removed commented statement
harshkhandeparkar Jan 6, 2024
a0c10a0
feat: added placement density as a debug option
harshkhandeparkar Jan 6, 2024
825e56e
feat: added median place density dataset; used in flow
harshkhandeparkar Jan 14, 2024
dde7a13
fix: always copy outputs to work/
harshkhandeparkar Jan 14, 2024
6434571
feat: delete ldo_place.txt in make clean
harshkhandeparkar Jan 14, 2024
3c8b121
fix: enabled failing at drc check again
harshkhandeparkar Jan 14, 2024
8510e12
fix: increased power transistor placement gap
harshkhandeparkar Jan 25, 2024
34b736f
feat: updated save_images.tcl to match upstream
harshkhandeparkar May 6, 2024
3a02d91
feat: call parse_rpt.py in make command
harshkhandeparkar May 6, 2024
6069d7c
fix: there is no parse_rpt.py so remove it
harshkhandeparkar May 6, 2024
d1114e3
fix: fixed drc errors :tada: :tada:
harshkhandeparkar May 23, 2024
03e706c
feat: cleaned up gds
harshkhandeparkar May 23, 2024
766ab22
fix: updated expected ldo DRC report
harshkhandeparkar May 23, 2024
8175831
fix: fixed the vref label
harshkhandeparkar Jun 5, 2024
53ef438
fix: changed prePEX netlist to use hvl transistors
harshkhandeparkar Jun 7, 2024
f7af5f4
fix: use the exact expected drc report
harshkhandeparkar Jun 7, 2024
b92503e
fix: changed PT_UNIT_CELL site to unithv
harshkhandeparkar Aug 22, 2024
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fix: removed pmos_2 from ldo_custom_net.txt
  • Loading branch information
harshkhandeparkar committed Aug 20, 2024
commit 031cdc3fddcc8c81aea0cc7ee116e2a5f25f1bf7
14 changes: 8 additions & 6 deletions openfasoc/generators/ldo-gen/tools/generate_verilog.py
Original file line number Diff line number Diff line change
Expand Up @@ -49,10 +49,12 @@ def update_custom_nets(blocksDir, arrSize):
"""Creates custom routes in ldo_custom_net.txt."""
with open(blocksDir + "/ldo_custom_net.txt", "w") as ldo_domain_insts:
# Always write comparator and pmos connections
if arrSize > INCLUDE_2_PMOS_ARRSIZE:
ldo_domain_insts.write("r_VREG\ncmp1 VREG\npmos_1 VREG\npmos_2 VREG\n")
else:
ldo_domain_insts.write("r_VREG\ncmp1 VREG\npmos_1 VREG\n")
ldo_domain_insts.write("r_VREG\ncmp1 VREG\npmos_1 VREG\n")

# The below code is commented since pmos_2 is commented in the Verilog
# if arrSize > INCLUDE_2_PMOS_ARRSIZE:
# ldo_domain_insts.write("pmos_2 VREG\n")

# write arrSize pt cells
for i in range(arrSize):
ldo_domain_insts.write("{pt_array_unit\[" + str(i) + "\]} VREG\n")
Expand Down Expand Up @@ -80,8 +82,8 @@ def update_area_and_place_density(flowDir, arrSize):
core_length = core_width = 260 + 20 * int(arrSize / 50)
vreg_width = die_width - 39

# place_density = round(0.3 + 0.1 * math.ceil((arrSize%50)/10),1)
place_density = 0.426
place_density = round(0.3 + 0.1 * math.ceil((arrSize%50)/10),1)
# place_density = 0.426

config_template = config_template.replace("@PARAM_DIE_WIDTH", str(die_width), 1)
config_template = config_template.replace("@PARAM_DIE_LENGTH", str(die_length), 1)
Expand Down