Draft: Chipathon2024 Mahowald-ers Regulated Cascoded Current Mirror block #349
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Current LVS result |
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Updated the Layout and decreased LVS Errors. Current LVS produces the following Errors The error now comes from the labels 'VCOPY ` Contents of circuit 1: Circuit: 'CM' Circuit was modified by parallel/series device merging. Contents of circuit 1: Circuit: 'CM' Circuit 1 contains 3 devices, Circuit 2 contains 3 devices. Final result: Logging to file "/tmp/tmpi4zjwy4q/CM_lvs.rpt" disabled Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes. Subcircuit pins:
Cell pin lists are equivalent. Cell CM (0) disconnected node: VCOPY
Netlists match uniquely with port errors. Subcircuit pins:
Cell pin lists for CM and CM altered to match. Final result: Top level cell failed pin matching. ` |
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Current Layout
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Finally Cleared LVS. Improvement suggestions on the layout (along with further technical checks) will be greatly appreciated. Specially need help with moving the components around to become DRC clean. DRC is still being checked. Next Goal is to get the Spice SIm going to extract the IV curve of this CM |
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current layout
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Schematic-wise, getting suggestions on the schematic code for these would be super helpful. Thanks in advance. (a) I'm not sure what's going on there. The Via from licon to met1 doesn't encompass the finger and the via to met 2 doesn't line up. The finger should be extended to fully enclose the via to met 1 track (blue), and the via between met1 and met2 (the red line) should be aligned with the previous via. I'm not sure how to achieve that in code. (b) We want to move the Vref pin and track to the other position. Not sure what port to use for that move. (c) The positioning of the pins (Vref, Vopy, and Vss) isn't good. They don't produce errors but would be great to bring them outside the well and make their location aligned and parametrized proper way. hope I am able to explain it in an understandable fashion.
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| def sky130_add_current_mirror_labels(CMS: Component, transistor_type: str = "nfet",pdk: MappedPDK =sky130) -> Component: # Re-introduce transistor_type | ||
| """Add labels to the current mirror layout for LVS, handling both nfet and pfet.""" | ||
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| met2_pin = (69, 16) |
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Can you use MappedPDK to make the labels pdk agnostic?
| from glayout.flow.spice.netlist import Netlist | ||
| from typing import Optional, Union | ||
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| def delete_files_in_directory(directory_path): |
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This is not related to the current mirror and should be in a different file if used for testing.
| except OSError: | ||
| print("Error occurred while deleting files.") | ||
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| global PDK_ROOT |
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It would be good to only export functions from this file.
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| # Generating only two transistors (one on each side): | ||
| source_netlist += f"XA {drain_net_A} {gate_net} {source_net} {bulk_net} {model_name} l={length} w={width} m={mtop} nf={fingers}\n" |
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There is no need to write spice to generate the netlist, it can be done programmatically. Refer to the opamp netlist generation code.
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| # @validate_arguments | ||
| def CurrentMirror( |
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Can this function name be changed to specify that it is a cascode current mirror?
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| return rename_ports_by_orientation(component_snap_to_grid(CurrentMirror)) | ||
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| def sky130_add_current_mirror_labels( |
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Can this be made pdk agnostic?
Team Mahowald-ers: PR for adding Regulated Cascoded Current Mirror block. This block will add a Cascode regulator block from this team's other PR for enhanced voltage swing.
Ref: DOI: 10.1109/AE54730.2022.9920096
This is an initial Commit and a Circuit (with description) will be added. Details of the goal of this PR can be found in this Gslides link presented in 05.09.2024 meeting
Current Status: A simple Current Mirror template is added. LVS is failing with Final result: Top level cell failed pin matching. Further comments will be added soon.