C route and other fixes

openfasoc/generators/glayout/glayout/flow/blocks/elementary/FVF/LVS

@@ -0,0 +1,41 @@
+
+Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
+Warning: Equate pins:  cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
+Warning: Equate pins:  cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__nfet_01v8         |Circuit 2: sky130_fd_pr__nfet_01v8         
+-------------------------------------------|-------------------------------------------
+1                                          |1                                          
+2                                          |2                                          
+3                                          |3                                          
+4                                          |4                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.
+Flattening unmatched subcell NMOS in circuit fvf (1)(2 instances)
+
+Class fvf (0):  Merged 3 parallel devices.
+Class fvf (1):  Merged 3 parallel devices.
+Subcircuit summary:
+Circuit 1: fvf                             |Circuit 2: fvf                             
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6->3)             |sky130_fd_pr__nfet_01v8 (6->3)             
+Number of devices: 3                       |Number of devices: 3                       
+Number of nets: 4                          |Number of nets: 4                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: fvf                             |Circuit 2: fvf                             
+-------------------------------------------|-------------------------------------------
+VIN                                        |VIN                                        
+Ib                                         |Ib                                         
+VOUT                                       |VOUT                                       
+VBULK                                      |VBULK                                      
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes fvf and fvf are equivalent.
+
+Final result: Circuits match uniquely.
+.

openfasoc/generators/glayout/glayout/flow/blocks/elementary/FVF/README.md

@@ -0,0 +1,37 @@
+## FLIPPED VOLTAGE FOLLOWER CELL
+
+```
+def  flipped_voltage_follower(
+        pdk: MappedPDK,
+        device_type: str = "nmos", 
+        placement: str = "horizontal",
+        width: tuple[float,float] = (3,3),
+        length: tuple[float,float] = (None,None),
+        fingers: tuple[int,int] = (1,1),
+        multipliers: tuple[int,int] = (1,1),
+        dummy_1: tuple[bool,bool] = (True,True),
+        dummy_2: tuple[bool,bool] = (True,True),
+        tie_layers1: tuple[str,str] = ("met2","met1"),
+        tie_layers2: tuple[str,str] = ("met2","met1"),
+        sd_rmult: int=1,
+        **kwargs
+        ) -> Component:
+    """
+    creates a Flipped Voltage Follower
+    pdk: pdk to use
+    device_type: either "nmos" or "pmos"
+    placement: either "horizontal" or "vertical"
+    width: (input fet, feedback fet)
+    length: (input fet, feedback fet)
+    fingers: (input fet, feedback fet)
+    multipliers: (input fet, feedback fet)
+    dummy_1: dummy for input fet
+    dummy_2: dummy for feedback fet
+    tie_layers1: tie layers for input fet
+    tie_layers2: tie layers for feedback fet
+    sd_rmult: sd_rmult for both fets
+    **kwargs: any kwarg that is supported by nmos and pmos
+```
+### GDS generated
+![gds generated](./fvfgds.png)
+

openfasoc/generators/glayout/glayout/flow/blocks/elementary/FVF/drc

@@ -0,0 +1,31 @@
+using default pdk_root: /usr/bin/miniconda3/share/pdk/
+Defaulting to stale magic_commands.tcl
+
+Magic 8.3 revision 464 - Compiled on Sat Mar  9 23:18:29 UTC 2024.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/tmp/tmp0t0g30yo/magic_commands.tcl" from command line.
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 6.0
+Library name: library
+Reading "fvf".
+[INFO]: Loading fvf
+
+Loading DRC CIF style.
+No errors found.
+[INFO]: DONE with /tmp/tmp0t0g30yo/fvf.rpt
+
+Using technology "sky130A", version 1.0.471-0-g97d0844
+
+Soft errors: 
+Error while reading cell "fvf" (byte position 118): Unknown layer/datatype in boundary, layer=64 type=44
+

openfasoc/generators/glayout/glayout/flow/blocks/elementary/FVF/fvf.py

@@ -0,0 +1,163 @@
+from glayout.flow.pdk.mappedpdk import MappedPDK
+from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk
+from gdsfactory.cell import cell
+from gdsfactory.component import Component
+from gdsfactory import Component
+from glayout.flow.primitives.fet import nmos, pmos, multiplier
+from glayout.flow.pdk.util.comp_utils import evaluate_bbox, prec_center, prec_ref_center, align_comp_to_port
+from glayout.flow.pdk.util.snap_to_grid import component_snap_to_grid
+from glayout.flow.pdk.util.port_utils import rename_ports_by_orientation
+from glayout.flow.routing.straight_route import straight_route
+from glayout.flow.routing.c_route import c_route
+from glayout.flow.routing.L_route import L_route
+from glayout.flow.primitives.guardring import tapring
+from glayout.flow.pdk.util.port_utils import add_ports_perimeter
+from glayout.flow.spice.netlist import Netlist
+from glayout.flow.primitives.via_gen import via_stack
+from gdsfactory.components import text_freetype, rectangle
+
+def fvf_netlist(fet_1: Component, fet_2: Component) -> Netlist:
+
+         netlist = Netlist(circuit_name='FLIPPED_VOLTAGE_FOLLOWER', nodes=['VIN', 'VBULK', 'VOUT', 'Ib'])
+
+         netlist.connect_netlist(fet_1.info['netlist'], [('D', 'Ib'), ('G', 'VIN'), ('S', 'VOUT'), ('B', 'VBULK')])
+         netlist.connect_netlist(fet_2.info['netlist'], [('D', 'VOUT'), ('G', 'Ib'), ('S', 'VBULK'), ('B', 'VBULK')])
+
+         return netlist
+
+def sky130_add_fvf_labels(fvf_in: Component) -> Component:
+
+    fvf_in.unlock()
+    # define layers`
+    met1_pin = (68,16)
+    met1_label = (68,5)
+    met2_pin = (69,16)
+    met2_label = (69,5)
+    # list that will contain all port/comp info
+    move_info = list()
+    # create labels and append to info list
+    # gnd
+    gnd2label = rectangle(layer=met1_pin,size=(0.5,0.5),centered=True).copy()
+    gnd2label.add_label(text="VBULK",layer=met1_label)
+    move_info.append((gnd2label,fvf_in.ports["B_tie_N_top_met_N"],None))
+
+    #currentbias
+    ibiaslabel = rectangle(layer=met2_pin,size=(0.5,0.5),centered=True).copy()
+    ibiaslabel.add_label(text="Ib",layer=met2_label)
+    move_info.append((ibiaslabel,fvf_in.ports["A_drain_bottom_met_N"],None))
+
+    # output (3rd stage)
+    outputlabel = rectangle(layer=met2_pin,size=(0.5,0.5),centered=True).copy()
+    outputlabel.add_label(text="VOUT",layer=met2_label)
+    move_info.append((outputlabel,fvf_in.ports["A_source_bottom_met_N"],None))
+
+    # input
+    inputlabel = rectangle(layer=met1_pin,size=(0.5,0.5),centered=True).copy()
+    inputlabel.add_label(text="VIN",layer=met1_label)
+    move_info.append((inputlabel,fvf_in.ports["A_multiplier_0_gate_N"], None))
+
+    # move everything to position
+    for comp, prt, alignment in move_info:
+        alignment = ('c','b') if alignment is None else alignment
+        compref = align_comp_to_port(comp, prt, alignment=alignment)
+        fvf_in.add(compref)
+    return fvf_in.flatten() 
+
+@cell
+def  flipped_voltage_follower(
+        pdk: MappedPDK,
+        device_type: str = "nmos", 
+        placement: str = "horizontal",
+        width: tuple[float,float] = (3,3),
+        length: tuple[float,float] = (None,None),
+        fingers: tuple[int,int] = (1,1),
+        multipliers: tuple[int,int] = (1,1),
+        dummy_1: tuple[bool,bool] = (True,True),
+        dummy_2: tuple[bool,bool] = (True,True),
+        tie_layers1: tuple[str,str] = ("met2","met1"),
+        tie_layers2: tuple[str,str] = ("met2","met1"),
+        sd_rmult: int=1,
+        **kwargs
+        ) -> Component:
+    """
+    creates a Flipped Voltage Follower
+    pdk: pdk to use
+    device_type: either "nmos" or "pmos"
+    placement: either "horizontal" or "vertical"
+    width: (input fet, feedback fet)
+    length: (input fet, feedback fet)
+    fingers: (input fet, feedback fet)
+    multipliers: (input fet, feedback fet)
+    dummy_1: dummy for input fet
+    dummy_2: dummy for feedback fet
+    tie_layers1: tie layers for input fet
+    tie_layers2: tie layers for feedback fet
+    sd_rmult: sd_rmult for both fets
+    **kwargs: any kwarg that is supported by nmos and pmos
+
+    Note- While using nmos, use with_dnwell=False
+    """
+
+    #top level component
+    top_level = Component(name="flipped_voltage_follower")
+
+    #two fets
+    device_map = {
+            "nmos": nmos,
+            "pmos":pmos,
+            }
+    device = device_map.get(device_type)
+
+    fet_1 = device(pdk, width=width[0], fingers=fingers[0], multipliers=multipliers[0], with_dummy=dummy_1, with_substrate_tap=False, length=length[0], tie_layers=tie_layers1, sd_rmult=sd_rmult, **kwargs)
+    fet_2 = device(pdk, width=width[1], fingers=fingers[1], multipliers=multipliers[1], with_dummy=dummy_2, with_substrate_tap=False, length=length[1], tie_layers=tie_layers2, sd_rmult=sd_rmult, **kwargs)
+    well = "pwell" if device == nmos else "nwell" 
+
+    fet_1_ref = top_level << fet_1
+    fet_2_ref = top_level << fet_2 
+
+    #Relative move
+    ref_dimensions = evaluate_bbox(fet_2)
+    if placement == "horizontal":
+        fet_2_ref.movex(fet_1_ref.xmax + ref_dimensions[0]/2 + pdk.util_max_metal_seperation()+1)
+    if placement == "vertical":
+        fet_2_ref.movey(fet_1_ref.ymin - ref_dimensions[1]/2 - pdk.util_max_metal_seperation()-1)
+
+    #Routing
+    viam2m3 = via_stack(pdk, "met2", "met3", centered=True)
+    drain_1_via = top_level << viam2m3
+    source_1_via = top_level << viam2m3
+    drain_2_via = top_level << viam2m3
+    gate_2_via = top_level << viam2m3
+    drain_1_via.move(fet_1_ref.ports["multiplier_0_drain_W"].center).movex(-0.5*evaluate_bbox(fet_1)[1])
+    source_1_via.move(fet_1_ref.ports["multiplier_0_source_E"].center).movex(1.5)
+    drain_2_via.move(fet_2_ref.ports["multiplier_0_drain_W"].center).movex(-1.5)
+    gate_2_via.move(fet_2_ref.ports["multiplier_0_gate_E"].center).movex(1)
+
+    top_level << straight_route(pdk, fet_1_ref.ports["multiplier_0_source_E"], source_1_via.ports["bottom_met_W"])
+    top_level << straight_route(pdk, fet_2_ref.ports["multiplier_0_drain_W"], drain_2_via.ports["bottom_met_E"])
+    top_level << c_route(pdk, source_1_via.ports["top_met_N"], drain_2_via.ports["top_met_N"], extension=1.2*max(width[0],width[1]), width1=0.32, width2=0.32, cwidth=0.32, e1glayer="met3", e2glayer="met3", cglayer="met2")
+    top_level << straight_route(pdk, fet_1_ref.ports["multiplier_0_drain_W"], drain_1_via.ports["bottom_met_E"])
+    top_level << c_route(pdk, drain_1_via.ports["top_met_S"], gate_2_via.ports["top_met_S"], extension=1.2*max(width[0],width[1]), cglayer="met2")
+    top_level << straight_route(pdk, fet_2_ref.ports["multiplier_0_gate_E"], gate_2_via.ports["bottom_met_W"])
+    try:
+	    top_level << straight_route(pdk, fet_2_ref.ports["multiplier_0_source_W"], fet_2_ref.ports["tie_W_top_met_W"], glayer1=tie_layers2[1], width=0.2*sd_rmult, fullbottom=True)
+    except:
+	    pass
+    #Renaming Ports
+    top_level.add_ports(fet_1_ref.get_ports_list(), prefix="A_")
+    top_level.add_ports(fet_2_ref.get_ports_list(), prefix="B_")
+    top_level.add_ports(drain_1_via.get_ports_list(), prefix="A_drain_")
+    top_level.add_ports(source_1_via.get_ports_list(), prefix="A_source_")
+    top_level.add_ports(drain_2_via.get_ports_list(), prefix="B_drain_")
+    top_level.add_ports(gate_2_via.get_ports_list(), prefix="B_gate_")
+    #add nwell
+    if well == "nwell": 
+        top_level.add_padding(layers=(pdk.get_glayer("nwell"),),default= 1 )
+
+    component = component_snap_to_grid(rename_ports_by_orientation(top_level))
+
+    component.info['netlist'] = fvf_netlist(fet_1, fet_2)
+
+    return component
+
+

openfasoc/generators/glayout/glayout/flow/placement/four_transistor_interdigitized.py

@@ -39,8 +39,8 @@ def generic_4T_interdigitzed(
     if with_substrate_tap:
         substrate_tap = tapring(pdk, enclosed_rectangle=pdk.snap_to_2xgrid(evaluate_bbox(toplvl.flatten(),padding=pdk.util_max_metal_seperation())))
         substrate_tap_ref = toplvl << movey(substrate_tap,destination=pdk.snap_to_2xgrid(toplvl.flatten().center[1],snap4=True))
+        toplvl.add_ports(substrate_tap_ref.get_ports_list(),prefix="substratetap_")
     # add ports
-    toplvl.add_ports(substrate_tap_ref.get_ports_list(),prefix="substratetap_")
     toplvl.add_ports(toprow.get_ports_list(),prefix="top_")
     toplvl.add_ports(bottomrow.get_ports_list(),prefix="bottom_")
     # flag for smart route